SAN FRANCISCO—Fabless ASIC company Open-Silicon Inc. has introduced new technologies to address design issues common to the 65- and 40-nm nodes. Depending on customer needs, Open-Silicon will use the PowerMAX, CoreMAX and VariMAX technologies to build better custom silicon by designing in lower power, increased performance and managed process variability, the company said.

"By combining the ASIC industry's only transistor-level optimization flow with techniques like back biasing, which are new to the ASIC space, Open-Silicon can build the best possible fully custom silicon in smaller process geometries," said Satya Gupta, vice president of engineering and co-founder of Open-Silicon, in a statement.

Open-Silicon (Milpitas, Calif.) said CoreMAX was created to build the fastest processor cores in the ASIC world. The technology comes out of the Open-Silicon acquisition of Zenasis Technologies in 2007 and uses more than two million lines of C++ software and several patented techniques to move beyond the limitations of traditional library-based ASIC design, the company said.

Built-in CoreMAX functions include design Boolean analysis and optimization, static timing, cell placement, route estimation, and simultaneous optimization at the logical, physical, and transistor levels, Open-Silicon said.

VariMAX addresses increasing process variability with a back biasing design approach where the bulk transistor node voltage is controlled so that fast, leaky parts are reined in by adaptive calibration of the silicon, Open-Silicon said.

PowerMAX emphasizes low power. Open-Silicon said it has already completed state-of-the-art 65-nm designs using power savings methods like low-power place-and-route, voltage islands, power gating, clock gating, and multi-Vt. PowerMAX adds to this foundation with four new technologies: transistor level transformations, back biasing, power recovery, and custom leakage signoff, the company said.

All products are available for design use today, Open-Silicon, said.