Mentor quadruples Veloce hardware emulation capacity

Venice, Florida — Mentor Graphics Corp. unveiled the Veloce Maximus product. At up to 512 million gates, the Veloce Maximus product was designed to offer the required capacity for effective functional verification.

Veloce Maximus is powered by the same technology as the current family of Veloce products, delivering megahertz-class verification speeds for both "target-less" simulation acceleration and in-circuit emulation applications.

"Veloce Maximus continues to realize the scalability of our Veloce architecture," said Eric Selosse, vice-president and general manager, Mentor Graphics Emulation Division. "We invested heavily to develop an architecture that meets the performance and capacity needs of our most demanding customers. Veloce Maximus is a significant milestone on our product roadmap, but we are also deep into the development of our next leap in emulation capacity and performance. We're driven to keep pace with our customers' needs." First customer shipment of Veloce Maximus is scheduled for January 2009. For product information on the Veloce platform, contact your Mentor Graphics sales representative, call 1-800-547-3000, or visit this website .

Veloce family offers competitive features
A complex testbench co-simulating on a workstation typically limits simulation acceleration to 10X or less. Veloce's Test Bench XPress (TBX) overcomes this performance barrier via comprehensive support of transaction-level testbenches driving accelerated transactors through a high-speed SCMI-2 interface. TBX cuts simulation runtimes from hours to seconds, with speedups of 10,000X witnessed on customer designs. In-circuit emulation is advanced by a complete array of iSolve solutions spanning multimedia, interfaces like PCI-Express, and processors from ARM and others. iSolve solutions make it simple to connect your design to the physical world, slashing setup time while delivering comprehensive verification.

Veloce's architecture supports 16-asynchronous clock domains to deliver accurate verification modeling capability. This allows users to emulate complex, real-world behavior, and to detect and debug difficult corner-case issues, such as cross-domain race-conditions and glitches that are easily missed by other platforms, detecting design errors prior to tape-out, and reducing project risk.

The Veloce Maximus product simultaneously provides full visibility into each and every net of a 500 million gate design without impacting capacity or performance. Simulation users expect this level of visibility and the Veloce Maximus product delivers. Saving and restoring the state of a design after the end of an initialization sequence can save billions of clock cycles of verification across multiple regression tests. Maximus also supports assertion-based debugging including 0-In from Mentor Graphics.