Solido launches process variation solution for transistor-level designers

Venice, Florida &@8212 Solido Design Automation has introduced a scalable and extensible solution for meeting design challenges created by process variations at nanometer feature sizes. The new Variation Designer solution enables designers to eliminate design losses resulting from over- and under-design. Furthermore, as process complexity increases and new variation effects arise at smaller geometries, Variation Designer allows designers to expand their capabilities by plugging in applications that are created to solve specific variation problems, without the need for re-integration with the design environment. Its use results in "right designs" that meet or exceed specifications, with minimized power/area and maximized yields in a shorter time than is possible with a traditional design flow.

The Variation Designer solution provides a way for chip designers to analyze, identify and fix the effects of process variations on their designs. It provides automatic capabilities to analyze and identify process variation-related failure mechanisms, but cedes control to designers to use the information in combination with their experience and knowledge to fix those problems in an interactive manner. The new solution strengthens Solido's global position as an industry leader in process variation solutions for transistor-level design. Variation Designer is the most recent version of Solido's EDA (electronic design automation) tools, and was developed through intense and detailed interaction with major Solido customers.

In conjunction with Variation Designer, Solido has released seven statistical variation applications. The statistical variation applications utilize a systematic and consistent True Corner based design methodology. This flow extends the familiar digital corner-based design methodology to account for process variation effects. True Corners account for global, local (mismatch) and environmental variations for a specific design, and accurately represent the manufacturing and operating variance that a design is subjected to. The released applications include such functionalities as Latin hypercube sampling and run-time feedback, corner discovery, statistical sweep/sensitivity analysis and high-sigma verification. Other applications, including additional ones for statistical variation effects and well proximity effects, will be made available in the future.

Variation Designer is extremely scalable and is able to handle the high-capacity requirements imposed by large circuits with thousands of active devices. It has been tightly integrated with the Cadence ADE (Analog Design Environment) and Spectre, and the Synopsys HSPICE, design flows, and will also support other design flows in the near future, including custom flows. The product and the initial seven statistical variation applications are now available from Solido Design Automation.