Mentor updates P&R tool with low-power features
4/6/2009 9:52 AM EDT
Mentor Graphics Corp. has added new features for low power IC implementation to its place and route platform.
The Olympus-SoC system now includes the following key technologies to address low power challenges:
Automated multi-voltage flow with support for Dynamic Voltage and Frequency Scaling (DVFS) to handle varying supply voltages and clock frequencies, and the capability to handle special cells such as level shifters and isolation cells.
Power-aware clock tree synthesis (CTS) with smart clock gate placement, slew shaping, register clumping and concurrent MCMM optimization.
Seamless concurrent optimization for both power states and timing, covering all operating modes and corners through all stages of the flow.
Unified Power Format (UPF)-based Netlist-to-GDSII flow including support for power state definition tables.
The Olympus-SoC system is architected to directly handle 100 million-plus gates in flat mode.
The low power capabilities are targeted for advanced technology processes and take advantage of the Olympus-SoC production-proven design-for-variability architecture that natively optimizes for variations in design modes, process corners and manufacturing.
Consequently, the Olympus-SoC customers are experiencing 2-3X faster design closure times, as well as a 30 percent power savings versus traditional solutions, according to Mentor Graphics.
The Olympus-SoC low-power platform offers true concurrent multi-corner, multi-mode (MCMM) power states and timing closure for optimal quality of results and fast turnaround time throughout the netlist-to-GDSII design flow.
Multi-voltage design, a mainstream technique to reduce total power, is a complex, time-consuming task. This is because many blocks operating at different voltages, or intermittently shut off, increases the number of power states, which compounds the already complex MCMM problem.
Incumbent place-and-route systems that do not have native MCMM capabilities are not able to efficiently handle the complexity of optimizing both power and timing concurrently, according to Mentor.
Olympus-SoC for low power design is available now.