EVE unveils scalable emulation system

PARIS — On the eve of the 46^th Design Automation Conference (DAC) in San Francisco, Calif., Emulation and Verification Engineering SA (Palaiseau, France) has introduced a scalable emulation system that is said to handle up to one-billion ASIC gates.

In comparison with previous generations, EVE said that its ZeBu-Server scalable emulation system offers a "high level of automation, short compile time, multi-user capabilities and greater execution speed." Its transactor catalog eases and accelerates the installation of the run-time environment.

EVE explained that ZeBu-Server targets all SoC verification requirements across the entire development cycle, from hardware verification, hardware/software integration to embedded software validation. It can be used as a multi-user, multi-mode accelerator/emulator with a typical performance of 10 megahertz on a 40-million gate design.

The ZeBu-Server compiler includes a multicore capability to break the linearity of the compile time on large designs. EVE claimed that, in early tests, the ZeBu-Server software compiled a 200-million gate design in less than 10 hours, and a one-billion gate design in less than 12 hours.

"ZeBu-Server is a breakthrough in emulation and acceleration," claimed Lauro Rizzatti, EVE-USA’s general manager and vice president of marketing. "It offers high-capacity, fast setup, unparalleled speed of execution and powerful design debugging. All coalesce to ease the transition from processor-based emulators and custom FPGA-based emulators."

Finally, EVE stated that ZeBu-Server, priced from $150,000, offers automated, fast and incremental compilation from SystemVerilog, Verilog and VHDL register transfer level (RTL) code. It includes complete RTL signal waveform dumping and support for SystemVerilog Assertions.