Calypto claims 5X IC verification capacity boost

Calypto Design Systems released SLEC 4.0, with up to five times the capacity of the previous version, and with tighter integration with high-level synthesis tools from Cadence Design Systems, Mentor Graphics, and Forte.

Calypto pioneered sequential logic equivalence checking when it announced its first version of SLEC nearly five years ago.

Featuring algorithmic enhancements to Calypto's patented word level solvers, the latest version of SLEC also includes dramatic improvement to SLEC's proprietary database that results in a reduced memory footprint while SLEC is running. Together, these advancements enable the tool to handle larger, more complex designs.

With version 4.0, SLEC users can fully verify designs with multiple, independent clocks. For example, SLEC RTL can verify that the relationship between two clocks (e.g. one clock is a multiple of another) is not disrupted by the manual introduction of sequential optimizations for power or performance by a designer. SLEC RTL can also now detect the illegal mixing of signals from different clock domains introduced by sequential transformations.

SLEC 4.0 qill be showcased at DAC 2009 next week.

Available now, Calypto's SLEC 4.0 runs on PC platforms running Linux. Pricing for a one-year, time-based license is as follows: SLEC System: $250,000; SLEC System-HLS (add on option to SLEC System): $50,000; SLEC RTL: $175,000; SLEC Pro: $125,000.