Synphony HLS creates optimized RTL for both ASIC and FPGA implementation, architecture exploration and rapid prototyping.

The Mathworks' M-language has been broadly adopted for algorithm exploration and design because it allows concise expression of behavior at an extremely high level of abstraction.

These M-code models are typically re-coded and re-verified at the RT Level (RTL) and in some cases in C/C++ for implementation and verification.

According to Synopsys, Synphony HLS allows designers to stay in their preferred algorithm modeling language, eliminating the need to re-code and re-verify models and enabling early system-level validation and verification.

Synphony HLS creates implementable RTL and C-models directly from high-level M-language code and the Synphony HLS-optimized IP model libraries. Using a constraint-driven fixed-point propagation feature, designers can derive fixed-point models from a synthesizable subset of high-level, floating-point M-code.

The Synphony HLS engine will then synthesize architecturally optimized RTL to meet area, speed and power goals.

In addition, Synphony HLS complements C/C++-based flows by generating C-models for system validation and early software development in virtual platforms.

Synphony HLS enables C-based verification and validation to start much earlier in the design cycle, according to Synopsys.

"Until now, there has not been an automated way to derive a coherent verification flow across abstraction levels nor an implementation flow with optimized output from the very popular M language," said Gary Meyers, vice president and general manager of the Synplicity Business Group at Synopsys.

Meyers said that Synphony was the first product generated since Synopsys bought Synplicity in 2008.

The Synphony HLS engine can synthesize optimized architectures for ASIC, FPGA, rapid prototyping or virtual platforms while maintaining coherent verification through all levels of the implementation flow.

For ASIC design Synphony HLS includes a new advanced timing estimation capability that automatically utilizes Design Compiler for automatic pipelining and timing closure for a given ASIC technology.

For FPGA design Synphony HLS includes timing and device-specific optimizations for FPGA families from Actel, Altera, Lattice and Xilinx. This includes optimized mapping to hardware multipliers, memories, shift registers and other hardware resources in today's FPGA devices.

For rapid prototyping Synphony HLS and Synopsys' Confirma rapid prototyping solutions let design teams create a pre-silicon prototype of their design and start high-performance algorithm validation and software development earlier in the design cycle.

Synphony HLS is in limited customer availability with general availability by the end of calendar year 2009.