Jasper unveils DFI formal verification proof kits

PARIS – Jasper Design Automation Inc. (Mountain View, Calif.) has released proof kits for the DFI (DDR-PHY) specification.

Jasper said the DFI proof kits are sets of properties, written in SystemVerilog, for verification of standard interface protocols. Each proof kit includes a Formal Testplan providing detailed instructions on verifying DFI designs, plus properties for the protocol that the JasperGold Verification System can prove against designs employing the specification. DFI solutions are used for cell phones, high-performance graphics and other memory-intensive applications.

Jasper specified that the DFI proof kits are now available with no additional charge to current licensees of Formal Testplanner.

Other Jasper Proof Kits include AMBA 4 with AMBA 4 AXI, AXI-Stream and AXI-Lite interfaces; LPDDR1, LPDDR2, DDR, DDR2 and DDR3 SDRAM; AHB and AHB Lite; APB; Ethernet MDIO; OCP-IP; PCI-Express.

The DFI specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the memory devices.

The DFI specification is being developed by expert contributors from recognized leaders in the semiconductor, IP and EDA industries.