Cadence defines Cortex-A15 MPCore implementation methodology

Cadence Design Systems Inc. said it is providing an optimized implementation methodology for the new ARM Cortex-A15 MPCore processor. The purpose is to offer mutual customers an immediate access to optimized implementation flow for designing Cortex-A15 MPCore-Based SoCs.

Cadence noted that the methodology results from the broadening of an existing collaboration with ARM to develop an optimized System Realization solution for ARM processors that will enable an end-to-end flow including a full set of interoperable tools, ARM processor and physical IP, services and methodology from embedded Linux to GDSII.

"Our early collaboration with the Cadence team has been instrumental in ensuring the adoption of the ARM Cortex-A15 processor by providing an implementation path to a broader set of ARM Partners," stated Eric Schorn, vice president of Marketing, Processor Division, ARM.

Schorn continued: "Combining Cadence’s expertise in deployment tools and methodology across a broad portfolio of ARM processors and physical IP enables our customers to get earlier access to a complete design flow. This collaboration resulted in a streamlined design cycle for our most advanced customers providing next-generation high-performance devices.”

The recently announced Cortex-A15 MPCore processor is claimed to deliver a 5x performance improvement over today's advanced smartphone processors, within a comparable energy footprint.

The Cortex-A15 MPCore processor is the latest member of the Cortex-A series of processors, ensuring full application compatibility with the other Cortex-A processors. This enables immediate access to an established developer and software ecosystem including Android, Adobe Flash Player, Java Platform Standard Edition (Java SE), JavaFX, Linux, Microsoft Windows Embedded, Symbian and Ubuntu, along with more than 700 ARM Connected Community members providing applications software, hardware and software development tools, middleware and SoC design services.