TSMC qualifies Synopsys' IC Validator for 40nm, 65nm

PARIS – Taiwan Semiconductor Manufacturing Company (TSMC) said it has qualified Synopsys' IC Validator physical verification tool for 40nm and 65nm interoperable DRC/LVS runsets.

TSMC's qualification of IC Validator brings the benefits of In-Design flow to the broad range of design teams utilizing TSMC’s 40nm and 65nm process technologies, companies said.

IC Validator, part of the Galaxy Implementation Platform, is a signoff DRC/LVS tool that has been architected for in-design physical verification at leading-edge process nodes. It delivers scalability for efficient utilization of available hardware, superior ease-of-use for the physical designer, and high programmability for easier runset development, according to Synopsys.


IC Validator and IC Compiler share data models and processing engines, resulting in an integrated In-Design physical verification flow designed to deliver signoff-level accuracy coupled with superior productivity.

Synopsys explained that, compared to the traditional “implement-then-verify” approaches, the In-Design flow avoids late-stage surprises and mitigates costly iterations between place-and-route and signoff. In-Design physical verification provides functionality such as incremental DRC, automatic error detection and correction, optimal metal-fill insertion and rapid ECO validation, all within the place-and-route environment, enabling physical design engineers to generate manufacturing-clean designs that should pass the final signoff check without difficulty, speeding overall time to tapeout.

Click here to access Synopsys' IC Validator datasheet.