Product Brief
Mentor claims comprehensive support for UVM 1.0
Anne-Francoise Pele2/23/2011 6:13 AM EST
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Mentor Graphics Corp. announced its comprehensive support for Accellera's Universal Verification Methodology (UVM) across a host of products including Questa advanced functional verification platform, the Questa MVC Verification IP library, the Veloce emulation platform and the Certe Testbench Studio tool.
EDA standards development organization Accellera said earlier this week it had approved version 1.0 of its Universal Verification Methodology (UVM) standard.
According to Accellera, UVM 1.0 fully qualifies the baseline features, corrects most of the known bugs and implements enhancement requests. Major new features include a phasing mechanism, a register package (derived from Verification Methodology Manual technology) and support for the Open SystemC Initiative's Transaction Level Modeling-2.0 (TLM-2.0) standard to model component transaction connectivity and communication, Accellera said.
Mentor said its Questa advanced functional verification platform offers native support for UVM by virtue of its industry-leading support of the IEEE Std 1800 SystemVerilog standard on which UVM is based. This support includes comprehensive language feature support, native single-kernel simulation and full functional debug of SystemVerilog and UVM.
The Questa Verification IP library has added native support for UVM. This allows users of UVM access to a comprehensive verification IP (VIP) solution that supports a wide range of industry-standard protocols without the need for any manual conversion, interoperability, or wrapper layers. The Questa Verification IP library improves verification coverage and helps speed the functional verification of ICs using industry-standard protocols.
The Veloce emulation platform fully supports the UVM. The primary advantage to companies using both the UVM/OVM and the Veloce platform is the ability to use a single transaction-based testbench for both simulation and emulation.
The Certe Testbench Studio tool helps verification engineers harness the power of UVM by guiding the development of testbenches and registers that are correct-by-construction. The Certe Testbench Studio tool also delivers deep insight into the testbench construction and functionality via UVM testbench visualization, multiple class relationship views, full testbench object browsers, and register management. The Certe Testbench Studio tool enables rapid creation, complete understanding, and documentation of UVM testbenches for the most complex designs.
Availability
UVM is available from Accellera at www.accellera.org. OVM users can download the UVM kit from www.uvmovmworld.org where information specific to current OVM users can help them accelerate the adoption of UVM.
EDA standards development organization Accellera said earlier this week it had approved version 1.0 of its Universal Verification Methodology (UVM) standard.
According to Accellera, UVM 1.0 fully qualifies the baseline features, corrects most of the known bugs and implements enhancement requests. Major new features include a phasing mechanism, a register package (derived from Verification Methodology Manual technology) and support for the Open SystemC Initiative's Transaction Level Modeling-2.0 (TLM-2.0) standard to model component transaction connectivity and communication, Accellera said.
Mentor said its Questa advanced functional verification platform offers native support for UVM by virtue of its industry-leading support of the IEEE Std 1800 SystemVerilog standard on which UVM is based. This support includes comprehensive language feature support, native single-kernel simulation and full functional debug of SystemVerilog and UVM.
The Questa Verification IP library has added native support for UVM. This allows users of UVM access to a comprehensive verification IP (VIP) solution that supports a wide range of industry-standard protocols without the need for any manual conversion, interoperability, or wrapper layers. The Questa Verification IP library improves verification coverage and helps speed the functional verification of ICs using industry-standard protocols.
The Veloce emulation platform fully supports the UVM. The primary advantage to companies using both the UVM/OVM and the Veloce platform is the ability to use a single transaction-based testbench for both simulation and emulation.
The Certe Testbench Studio tool helps verification engineers harness the power of UVM by guiding the development of testbenches and registers that are correct-by-construction. The Certe Testbench Studio tool also delivers deep insight into the testbench construction and functionality via UVM testbench visualization, multiple class relationship views, full testbench object browsers, and register management. The Certe Testbench Studio tool enables rapid creation, complete understanding, and documentation of UVM testbenches for the most complex designs.
Availability
UVM is available from Accellera at www.accellera.org. OVM users can download the UVM kit from www.uvmovmworld.org where information specific to current OVM users can help them accelerate the adoption of UVM.
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