FPGA embedded intelligent IP enables ultra-fast Flash programming

Fully integrated, the ChipVORX IP enables the automatic recognition of the structural connections between the Flash target and the FPGA, as well as the succeeding script file generation. The programming is based on a standardised IEEE1149.1 TAP (Test Access Port) and can be executed on each run time station without further options. Thereby, Gang applications are supported. The ChipVORX IP is independent of the target to be programmed, so there are no restrictions on the Flash type. In addition to serial Flash, parallel NOR and NAND Flash incl. bad block handling is supported. In practice, the ChipVORX IP achieves drastic accelerations for bigger FPGA types compared to standard Boundary Scan programming procedures. Whilst typical values for parallel Flash are between 10 and 15 times, the factor for serial Flash achieves a size of 100 times and even higher. The acceleration is only limited by the Flash internal programming speed.

Currently, the ChipVORX models for Flash programming are available for all Altera and Xilinx FPGA families, additional ones are under development. Using the IP does not require expert background knowledge nor special FPGA tools or programmers. The new ChipVORX IP models are supported as standard starting from System Cascon version 4.5.4 and are activated by the licence manager like the system software.

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