Product Brief
Cypress release PSoC Creator 2.0
Brian Bailey9/22/2011 3:58 PM EDT
Comment
Dr DSP
There seem to be alot of applications that don't require 168MHz and the PSoC ...
jg_
Cypress has just released version 2.0 of their PSoC Creator Design Environment. This is an interesting tool in that it follows my DAC 2010 prediction regarding the four way merger of hardware and software, tools and IP as we move towards successful ESL tools. PSoC Creator was already a tool that merged the notion of tool and IP, and with the 2.0 release they have done that even more. They have also started the merge between hardware and software although this has a ways to go yet before I would say they are fully integrated. But let’s back up a bit.
PSoC is a programmable device family where each device contains a processor, some configurable digital parts and some configurable analog parts. All of these are stitched together by programmable interconnect. The goal of their Creator tool is to hide all of the implementation details from the user. In a BDTI study conducted in early 2010, back-end layout and route was the number one issue for flows based on FPGAs.
Hiding the back-end allows the user to think about the design and not the silicon or even the hardware blocks involved. It uses a schematic user interface and a simple intuitive configuration editor. The library currently contains 147 components and two or three new ones are added every couple of months.
In the 2.0 release they have also integrated Keil MicroVision which enables device firmware to be created and built for the PSoC family and fully kept in sync with configuration changes made in the design. They see this as a very necessary step because the sophistication of these devices has gone from being a one-man show type design, so a group effort and this requires more co-operation and control of the data as it gets generated throughout the design process.
Brian Bailey – keeping you covered
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PSoC is a programmable device family where each device contains a processor, some configurable digital parts and some configurable analog parts. All of these are stitched together by programmable interconnect. The goal of their Creator tool is to hide all of the implementation details from the user. In a BDTI study conducted in early 2010, back-end layout and route was the number one issue for flows based on FPGAs.
Hiding the back-end allows the user to think about the design and not the silicon or even the hardware blocks involved. It uses a schematic user interface and a simple intuitive configuration editor. The library currently contains 147 components and two or three new ones are added every couple of months.
Figure 1: Schematic entry
Figure 2: Configuring IP elements
In the 2.0 release they have also integrated Keil MicroVision which enables device firmware to be created and built for the PSoC family and fully kept in sync with configuration changes made in the design. They see this as a very necessary step because the sophistication of these devices has gone from being a one-man show type design, so a group effort and this requires more co-operation and control of the data as it gets generated throughout the design process.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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jg_
9/22/2011 6:56 PM EDT
There are also downsides to the 'all things to all users' approach :
The PSoC Creator build times are glacial - there are so many software jugglers involved.
The IP components may be flexible, but sadly they too are rather slow. Their specs give 15MHz for 16 bit counters. This beta (select customers only) release of v2.0 claims 20% better routing, but that's only 18MHz...
Contrast that with a STM32F4, which claims 168MHz 32 bit counters (and much more Flash/Ram/CPU/FPU for similar prices...)
There also seems to be a significant silicon cost to the 'all things' approach. PSoC parts are not cheap, and may yet suffer the FPSlic/Triscend disease.
It is looking faster and cheaper, to deploy two focused parts.
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Dr DSP
9/23/2011 11:15 PM EDT
There seem to be alot of applications that don't require 168MHz and the PSoC parts have been around long enough to make the Triscend disease unlikely. I do like the fact that the tools are integrating TOWARD the IDE and away from the FPGA place and route flows.
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