Product Brief
Arasan Chip Systems unveils mixed-signal USB 2.0 PHY IP
Paul Buckley10/19/2011 10:39 PM EDT
Comment
Dr DSP
Seems like a solid move by Arasan. USB is a common interface on the systems ...
Arasan Chip Systems, Inc., has introduced the
company's USB 2.0 PHY IP. The USB 2.0 PHY comprises a complete on-chip
physical transceiver solution optimized for low power consumption,
minimal die area, and high data throughput.
The USB 2.0 PHY features fully integrated Electrostatic Discharge (ESD) protection, full support for OTG, device, hub and host functionality.
The USB 2.0 PHY features fully integrated Electrostatic Discharge (ESD) protection, full support for OTG, device, hub and host functionality.
The core was developed by Mentor Graphics Corporation and proven in silicon in the SMIC 130 nm process. Arasan has licensed the complete core and associated technology from Mentor Graphics and Arasan will support and develop the technology using its own analog mixed signal design team.
"Acquiring this high-quality silicon-proven PHY core that successfully passed the USB plug-fest process has saved us a tremendous amount of development time." said Prakash Kamath, Vice President of Engineering for Arasan. "Demand for USB 2.0 products continues to be robust."
"For reasons unrelated to the USB market, we decided that the USB PHY business was not consistent with Mentor's overall strategy. We are pleased to have Arasan carrying this technology and our investment legacy forward." said Aaik van der Poel, Business Unit Manager, Continuing Products Division, Mentor Graphics. "During the development effort we carefully constructed this IP to be compatible with standard CMOS processes for ease of porting and qualified it through the USB-IF plug fest methodology."
The Arasan USB 2.0 PHY IP core is a high speed USB transceiver for use with host, embedded host, On-the-Go (OTG) and function controllers. Compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, the Arasan USB 2.0 PHY integrates high speed mixed-signal circuits to support USB High-Speed (HS) traffic at 480 Mbps and is backward-compatible with 12 Mbps Full-Speed (FS) and 1.5 Mbps Low-Speed (LS) data rates.
The USB 2.0 PHY IP is delivered in a GDSII format targeted for a specific process technology library. Because the design was done with standard CMOS process technology in mind it can easily be ported to many foundry/process technology combinations.
The USB 2.0 PHY joins the suite of other Arasan USB products including USB 2.0 Device, Hub, OTG, embedded Host, HSIC PHY and USB 3.0 Device.
The Arasan USB 2.0 PHY IP solution, including IP core, verification IP and documentation is available immediately for licensing.
Visit Arasan at www.arasan.com
This article originally appeared on EETimes Europe.
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Dr DSP
11/25/2011 2:47 PM EST
Seems like a solid move by Arasan. USB is a common interface on the systems Arasan targets so a bundle purchase should be an easy sale.
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