Product Brief
OCP-IP Delivers Enhanced Transaction Generator Package
Brian Bailey11/3/2011 11:56 AM EDT
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Open Core Protocol International Partnership (OCP-IP) has announced a new version of their Transaction Generator (TG), a transaction level (TL) SystemC simulator for benchmarking network-on-chips (NoCs) used in multiprocessor system-on-chip (SoC) applications. The latest version has added what they call an Accurate Dynamic Random-Access Memory Model (ADM) package. The ADM is a configurable, transaction-level model for Dynamic Random-Access Memories (DRAMs). It considers the major delay parameters of real DRAMs and imitates their realistic timing behavior by capturing access dependencies.
The TG can generate traffic for network-on-chip according to abstract software and hardware workload models. Utilizing this tool makes simulation of larger systems substantially faster and the results obtained at this higher level can be accurately used in initial estimates when selecting and fine-tuning NoCs. During simulation the TG measures performance metrics from the application and platform models, and from the traffic routed through network-on-chip.
The newly added DRAM executable can be used to test the delay and throughput of the memory subsystem for certain traffic flows. Integrated memory model enables two additional modeling features for TG: cache misses and shared-memory communication. Hence, the models can more accurately represent the performance of systems and enable a realistic evaluation of Networks on Chip. The package includes also a basic set of nine (9) traffic models from the multimedia and telecommunication domain.
The TG plus DRAM Models are now freely available to both OCP-IP members and non-members alike through GNU LGPL, and is an ideal addition to all system-level designers evaluating various interconnection solutions in a simulation model of a real, complex system. It can also be used to simulate IP blocks before real implementations are available which enables the design of interconnect and implementation of IP blocks and SW for processors to advance in parallel, saving time, resources, and ensuring a faster time-to-market.
The Transaction Generator and DRAM model kit were developed by Tampere University of Technology and Royal Institute of Technology (KTH) in conjunction with members of OCP-IP's Network on Chip Benchmarking working group including: Boston University, University of British Columbia, Carnegie Melon University, Washington State University, and Transylvania University in cooperation with industry members of the OCP-IP.
To download a copy of the Transaction Generator see, http://www.ocpip.org/tg_package.php
The Network on Chip Benchmarking Working Group has also issued an open call for Benchmarks to be distributed to researchers. NoC researchers may submit benchmarks from any application domain to be included. For more information on the call for benchmarks, please see http://www.ocpip.org/ocpspec_call_for_benchmarks.php
Institutions interested in joining the work of OCP-IP's Network on Chip Benchmarking Working Group should contact admin@ocpip.org
The TG can generate traffic for network-on-chip according to abstract software and hardware workload models. Utilizing this tool makes simulation of larger systems substantially faster and the results obtained at this higher level can be accurately used in initial estimates when selecting and fine-tuning NoCs. During simulation the TG measures performance metrics from the application and platform models, and from the traffic routed through network-on-chip.
The newly added DRAM executable can be used to test the delay and throughput of the memory subsystem for certain traffic flows. Integrated memory model enables two additional modeling features for TG: cache misses and shared-memory communication. Hence, the models can more accurately represent the performance of systems and enable a realistic evaluation of Networks on Chip. The package includes also a basic set of nine (9) traffic models from the multimedia and telecommunication domain.
The TG plus DRAM Models are now freely available to both OCP-IP members and non-members alike through GNU LGPL, and is an ideal addition to all system-level designers evaluating various interconnection solutions in a simulation model of a real, complex system. It can also be used to simulate IP blocks before real implementations are available which enables the design of interconnect and implementation of IP blocks and SW for processors to advance in parallel, saving time, resources, and ensuring a faster time-to-market.
The Transaction Generator and DRAM model kit were developed by Tampere University of Technology and Royal Institute of Technology (KTH) in conjunction with members of OCP-IP's Network on Chip Benchmarking working group including: Boston University, University of British Columbia, Carnegie Melon University, Washington State University, and Transylvania University in cooperation with industry members of the OCP-IP.
To download a copy of the Transaction Generator see, http://www.ocpip.org/tg_package.php
The Network on Chip Benchmarking Working Group has also issued an open call for Benchmarks to be distributed to researchers. NoC researchers may submit benchmarks from any application domain to be included. For more information on the call for benchmarks, please see http://www.ocpip.org/ocpspec_call_for_benchmarks.php
Institutions interested in joining the work of OCP-IP's Network on Chip Benchmarking Working Group should contact admin@ocpip.org
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