CAST introduced UDP hardware IP block

A new core from semiconductor intellectual property (IP) provider CAST, Inc. the UDPIP, is a hardware implementation of the User Datagram Protocol (UDP), part of the Internet Protocol Suite (TCP/IP) for data transfer over Ethernet.

UDP is a fast, simple, transport layer protocol that works without the handshaking and error correction of the more rigorous Transmission Control Protocol (TCP). This makes UDP good for applications like video or audio streaming, where receiving most of the data packets on time matters more than receiving every single packet. For example, the GigE Vision, ONVIF, and PSIA standards for IP-based cameras all incorporate UDP.

Implementing the UDP/IP stack in hardware saves millions of instructions per second that a host processor otherwise spends on UDP framing and checksum validation. Furthermore, UDP's direct, processor-free connection to media encoders and decoders eliminates the need to temporarily store streaming media data, significantly simplifying bus and memory arbitration, lowering design complexity, and reducing power consumption for streaming-capable SoCs.

The CAST UDPIP core supports a superset of typical UDP/IP functions and is configurable for transmit, receive, or both (full-duplex). It works with any 10/100/1000 Mbit Ethernet MAC transceiver, including FPGA MACs from Altera® and Xilinx® and synthesizable versions such as the CAST MAC-1G core. Performance suitable for 10 gigabit Ethernet (10GbE) has been achieved in some ASIC implementations. Integrating the core in system-on-chip designs is made easier through support for industry-standard streaming and bus interfaces.

Silicon implementation results indicate that this uses just 1,000 slices for the receive function on a Xilinx Virtex-5 device. (See more sample results online.)

UDPIP Core Features & Availability
The core transmits and receives UDP packet data messages to one (unicast) or more (broadcast) targets on an Ethernet LAN, using IPv4 without packet fragmentation (DHCP support is optional). It generates and validates outgoing and incoming checksums; Ethernet CRC error correction is an option.

Trouble-free network operation is ensured via run-time programmable parameters (IP and MAC addresses, ports) and both the critical for multiple-access networks ARP (Address Resolution Protocol) and Ping (the Echo Request and Reply Messages of the Internet Control Message Protocol, ICMP) for testing network connectivity.

The core can connect directly to media codecs via dedicated streaming-capable interfaces or via an arbitrated system bus. Available interfaces include AMBA AXI4-Stream and Avalon®-ST for streaming packet data, and the AMBA AHB, Avalon-MM, and Wishbone system bus interfaces.
The CAST UDPIP core is available now in Verilog or as an optimized netlist for Altera and Xilinx FPGAs. Integration with MAC cores from CAST, FPGA vendors, or other sources is available. Integration with CAST compression cores is also available, to make it even easier for SoC designers to incorporate video streaming over IP networks.

Brian Bailey – keeping you covered

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