Product Brief
New Ceva DSP powers LTE and Wi-Fi 802.11ac reference architectures
Brian Bailey2/21/2012 11:51 AM EST
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There was a flurry of press releases from Ceva today centered on the introduction of their new DSP architecture framework – the XC4000. Ceva is excited about this core because of its power efficiency and that it utilizes an innovative instruction set to enable highly complex, software-based baseband processing which otherwise could only be accomplished with dedicated hardware. Illustrating this, the CEVA-XC4000 delivers a 5X performance improvement over the CEVA-XC323 DSP for LTE-A processing, while consuming 50% less power.
The CEVA-XC4000 architecture is offered in a series of six fully programmable DSP cores. They incorporate power-oriented enhancements, including CEVA’s second generation Power Scaling Unit (PSU 2.0) which dynamically supports clock and voltage scaling with fine granularity within the processor, memories, buses and system resources. The architecture also utilizes Tightly Coupled Extensions (TCE) to deliver inter-connected power-optimized coprocessors and interfaces for the implementation of critical PHY functions, further reducing power consumption. A rebalanced pipeline with low-level module isolation is also highly optimized for power.
The CEVA-XC4000 incorporates enhanced system-level mechanisms, queues and interfaces to deliver performance, faster connectivity, higher bandwidth, lower latency and better PHY control. The architecture offers two distinct inter-mixable high-precision instruction sets, supporting the most advanced 4x4 and 8x8 MIMO algorithms.
The CEVA-XC4000 DSP architecture is supported by CEVA-Toolbox™, a complete software development environment, incorporating Vec-C™ compiler technology for advanced vector processors, enabling the entire architecture to be programmed in C-level. An integrated simulator provides verification of the entire system including the memory sub-systems. In addition, CEVA-Toolbox includes libraries, a graphical debugger, and a complete optimization tool chain named CEVA Application Optimizer. The Application Optimizer enables automatic and manual optimization applied in the C source code.
CEVA has also announced complete reference architectures targeting complex communication standards, including LTE-A Rel-10 and Wi-Fi 802.11ac supporting up to 1.7 Gbps, in collaboration with CEVA-XCnet partners mimoOn and Antcor. These reference architectures are complemented with highly optimized software libraries for LTE-A and Wi-Fi.
With the new 802.11ac Wi-Fi standard yet-to-be ratified, and numerous other derivatives including 802.11af, 802.11p and Wi-Fi Direct, this software-based approach enables complete flexibility to address changes in the standard and support for various use-cases through software updates. This Wi-Fi reference architecture is ideal for cost-efficient, ultra-low power applications, requiring as small as 1.5 sqmm die area at a 28nm process.
The reference architecture addresses both the PHY and Lower-MAC layers in software with minimal hardware acceleration. The solution supports the full channel bandwidth up to 160MHz and offers maximal throughput of 867Mbps using a 4x2 MIMO beam-forming with 256-QAM modulation support, and can be scaled to support up to 1.7Gbps. The reference architecture supports a wide range of Wi-Fi standards, including 802.11a/b/g/n/ac, providing customers with ample headroom to add additional features and functionality on the same platform and further differentiate their product offering.
For LTE-Advanced (LTE-A) and legacy cellular modems the reference architecture leverages power management and system partitioning to enable a software-based LTE-A solution requiring as small as 3.4 sqmm die area and 100mW at a 28nm process. A complete set of optimized LTE-A libraries developed by CEVA is incorporated, significantly accelerating time-to-market and reducing development efforts for customer SoCs. The reference architecture supports the most demanding use cases, including the maximum throughput of LTE-A Rel-10 up to CAT-7. For example, it supports carrier aggregation of up to two carrier components to a total of 40MHz channel bandwidth, with spatial multiplexing of 8x4 MIMO, 300 Mbps downlink and 100 Mbps on the uplink.
For more information visit http://www.ceva-dsp.com/CEVA-XC4000.html
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
The CEVA-XC4000 architecture is offered in a series of six fully programmable DSP cores. They incorporate power-oriented enhancements, including CEVA’s second generation Power Scaling Unit (PSU 2.0) which dynamically supports clock and voltage scaling with fine granularity within the processor, memories, buses and system resources. The architecture also utilizes Tightly Coupled Extensions (TCE) to deliver inter-connected power-optimized coprocessors and interfaces for the implementation of critical PHY functions, further reducing power consumption. A rebalanced pipeline with low-level module isolation is also highly optimized for power.
The CEVA-XC4000 incorporates enhanced system-level mechanisms, queues and interfaces to deliver performance, faster connectivity, higher bandwidth, lower latency and better PHY control. The architecture offers two distinct inter-mixable high-precision instruction sets, supporting the most advanced 4x4 and 8x8 MIMO algorithms.
The CEVA-XC4000 DSP architecture is supported by CEVA-Toolbox™, a complete software development environment, incorporating Vec-C™ compiler technology for advanced vector processors, enabling the entire architecture to be programmed in C-level. An integrated simulator provides verification of the entire system including the memory sub-systems. In addition, CEVA-Toolbox includes libraries, a graphical debugger, and a complete optimization tool chain named CEVA Application Optimizer. The Application Optimizer enables automatic and manual optimization applied in the C source code.
CEVA has also announced complete reference architectures targeting complex communication standards, including LTE-A Rel-10 and Wi-Fi 802.11ac supporting up to 1.7 Gbps, in collaboration with CEVA-XCnet partners mimoOn and Antcor. These reference architectures are complemented with highly optimized software libraries for LTE-A and Wi-Fi.
With the new 802.11ac Wi-Fi standard yet-to-be ratified, and numerous other derivatives including 802.11af, 802.11p and Wi-Fi Direct, this software-based approach enables complete flexibility to address changes in the standard and support for various use-cases through software updates. This Wi-Fi reference architecture is ideal for cost-efficient, ultra-low power applications, requiring as small as 1.5 sqmm die area at a 28nm process.
The reference architecture addresses both the PHY and Lower-MAC layers in software with minimal hardware acceleration. The solution supports the full channel bandwidth up to 160MHz and offers maximal throughput of 867Mbps using a 4x2 MIMO beam-forming with 256-QAM modulation support, and can be scaled to support up to 1.7Gbps. The reference architecture supports a wide range of Wi-Fi standards, including 802.11a/b/g/n/ac, providing customers with ample headroom to add additional features and functionality on the same platform and further differentiate their product offering.
For LTE-Advanced (LTE-A) and legacy cellular modems the reference architecture leverages power management and system partitioning to enable a software-based LTE-A solution requiring as small as 3.4 sqmm die area and 100mW at a 28nm process. A complete set of optimized LTE-A libraries developed by CEVA is incorporated, significantly accelerating time-to-market and reducing development efforts for customer SoCs. The reference architecture supports the most demanding use cases, including the maximum throughput of LTE-A Rel-10 up to CAT-7. For example, it supports carrier aggregation of up to two carrier components to a total of 40MHz channel bandwidth, with spatial multiplexing of 8x4 MIMO, 300 Mbps downlink and 100 Mbps on the uplink.
For more information visit http://www.ceva-dsp.com/CEVA-XC4000.html
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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