Avery DDR4 and DFI-PHY Verification IP

A suite of verification IP gives memory suppliers the tools they need to develop products for the DDR4 standard. The Avery Design Systems DDR-Xactor VIP provides DDR and LPDDR memory models and a complete DFI-PHY verification solution.

The IP includes:

• SDRAM memory chip and DIMM models
• DFI-PHY model
• Simple AXI-based memory controller model
• Compliance test suite
• Timing and protocol checks
• DFI and JEDEC protocol analyzer trackers

Models and compliance test suites are developed in SystemVerilog and support UVM, OVM, and VMM environments.  

Memory models support all speed modes and configurations, with parameter files for the major SDRAM vendors including Samsung, Hynix, and Micron. Memory models support a full SDRAM/DIMM user API with a variety of advanced features such as:

• Clock jitter
• Random DQS timing
• CRC/parity error injection
• Backdoor access to DDR chip and DIMM memory locations
• Callbacks and analysis ports for memory access and state transitions

DFI-compliant PHY verification is performed using the Avery-provided plug-and-play test bench and compliance test suite focusing on DFI functional requirements such as reset, write leveling, refresh, power down, frequency change, and PHY update.

SoC/memory controller verification is performed using the Avery DDR chip/DIMM memory models to test memory controller functions such as memory refresh and control modes such as DDR4's PDA and modereg readout.

DDR-Xactor supports the JEDEC SDRAM standards including DDR4 (version 0.9) and DDR3, the JEDEC mobile memory standards including LPDDR3 and LPDDR2, and DRAM module standards.  DDR-Xactor also supports the DFI-PHY 2.1 and 3.0 standards.

For more information, go to www.avery-design.com.


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