Soft errors can cause headaches at smaller geometries

Soft errors are caused by the interaction of natural radiation with silicon. They can happen at any time and at any location during the operational life of the device.  The smaller the technology, the higher the sensitivity of designs to soft errors, that cannot be eliminated using classic post-manufacturing reliability techniques such as burn-in or stress test.  Typically expressed as the number of failures in time (FIT), the SER for IC design is growing as geometries shrink and now impacts many fabless companies and independent device manufacturers (IDMs).

Also to be expected, structures such as memories are more susceptible to this kind of error. I wrote about this in my EDN column “Practical Chip Design” back in December 2011.

IROC has been in the soft error business for a decade, developing simulation expertise and tools while also providing test and analysis services. TFIT 2 predicts the SER FIT of any CMOS digital cell. The company’s algorithms capture the complexity of cosmic rays interactions with silicon using the cell SPICE netlist and layout as design input, and the transistor model and process response model provided by foundries as technology input. The SOCFIT tool platform is a prediction and analysis tool that links raw cell soft error rate (SER) to circuit SER and system SER. SOCFIT 3 allows chip architects to assess the FIT rate early in the design (RTL, gate netlist), budget mitigation to reach the FIT goal, analyze quickly the effects of derating or masking, optimize the mitigation, and report the FIT rate to their customers with solid technical explanations.

I asked the company about error rates. They provided the following graph that shows that while the memory bitcell soft error rate sensitivity is improving, the overall failure rate in a system is increasing as the process node decreases.

TSMC 40G and 28HP SER process models are available immediately from TSMC. Additional models for other process nodes are under development.

For more information about IROC Technologies you should visit their website.

Brian Bailey – keeping you covered

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