Sigrity tackles chip I/O model extraction problem

Sigrity has introduced XcitePI IO Interconnect Model Extraction. The tool generates chip IO power/ground and signal interconnect models for system-level analysis of high-speed channels and buses. Built-in IO quality assessment capabilities enable designers to quickly check IO power/ground robustness and signal electrical performance to identify potential design defects.

Dr. Jiayuan Fang, president of Sigrity, explained that prior to Sigrity’s XcitePI IO Interconnect Model Extraction technology, simultaneous switching output (SSO) analysis was either unduly pessimistic or overly optimistic. The lack of IO interconnect models made the simulated power/ground noise at driver and receiver sides unpredictable, especially when a large number of drivers switch simultaneously. Accurate models of chip IO interconnects that fully represent the distributed nature of power, ground and signals as well as their electromagnetic coupling effects were not available in commercial EDA flows.

Power analysis tools often consider only the resisteive effects of the grid, while some include capacitive and limited inductancve coupling effects. When these are taken into account, simulation speeds can suffer. Xcite believes they have solved these problems.



According to Sigrity, the chip IO models created by XcitePI IO Interconnect Model Extraction offer both high resolution and compact size to ensure accuracy and efficiency. These models can be used in conjunction with SPICE-compatible circuits for system-level simulations. Taking chip layout data in GDSII or LEF/DEF formats, the XcitePI IO Interconnect Model Extraction tool generates a SPICE netlist that consists of a fully distributed IO power/ground model and IO signal connections from IO cells to bumps. It accounts for all coupling between the power, ground and signals on the chip, the distributed capacitance associated with the power and ground systems, and on-chip decoupling capacitors connected to the power and ground systems. The resulting chip IO interconnect model includes external terminals on the bump side with Sigrity’s Model Connection Protocol (MCP) header information for easy connection to IC package models. Similarly, the model includes external terminals at the IO cell level to streamline connection with targeted driver/receiver models. Thus XcitePI IO Interconnect Model Extraction provides precise interconnect models for chips, packages and boards – an essential requirement for accurate signal integrity analysis of high-speed channels and buses.

The tool also enables quick assessment of power and ground quality along with signal performance at every IO cell. Graphical representations of electrical performance at each cell help users quickly identify weak or problematic physical areas and perform what-if analysis.

Pricing and Availability
XcitePI IO Interconnect Model Extraction is available on Windows and Linux platforms with pricing starting at $108,000 for a 3-year license.

Brian Bailey – keeping you covered

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