Cadence Design Systems
Full line EDA supplierProducts
:Incisive Enterprise Simulator
Verifies power intent with no disruption or modification to the functional verification environment. Low-power verification includes modeling power domains, modes and power cells (isolators etc.) from the power intent file. Assertions to test the low-power behavior, and power-specific coverage metrics are inferred from the power intent file. Power-aware mixed-signal simulation is also available with Virtuoso AMS Designer. Palladium III and XP Emulators
Supports power-aware execution from the CPF file orders of magnitude faster than simulation, and well as power estimation and profiling with the Dynamic Power Analysis capability. Conformal Low Power
Formally verifies power intent in context of the design. Combines low-power equivalence checking with rigorous structural and functional checks to enable full-chip verification of power-efficient designs. Encounter RTL Compiler
Implements a wide range of advanced low-power techniques, such as power shutoff (PSO), and multi-supply voltage (MSV). Ensures that logic restructuring and gate-level optimization respect power-domain boundaries without invalidating power intent rules. Encounter Test
For Design For Test (DFT), Encounter Test ensures scan controllability and observability in all power modes by synthesizing a power-aware test access manager from the power intent. Dynamic power during ATPG can be optimized during scan and capture phases by limiting switching activity, without unduly extending test time. Encounter Digital Implementation System
Supports all major low power techniques such as power shutoff (PSO), multi-supply voltage (MSV), dynamic voltage and frequency scaling (DVFS), substrate biasing, and more. These capabilities are available for full digital or mixed-signal implementation. Virtuoso Schematic Editor
Supports import of digital blocks with CPF files, and generation of CPF for analog/mixed-signal designs and macros, to enable integration and verification of mixed-signal low-power designs. Encounter Power System
Power analysis which helps designers debug and verify that power and IR drop constraints are met. Integrated with Encounter Digital Implementation System to improve design convergence, it is part of a complete Cadence signoff solution that includes Encounter Timing System and Encounter Library Characterizer.
Website: http://www.cadence.com/solutions/lp/Pages/Default.aspxRelated articlesPower Intent Formats: Light at the End of the Tunnel?Opinion: What Comes After Power Intent Formats?Hierarchical methods for power intent specification
Building predictability into your low-power design flow
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