Synopsys power products

Synopsys
Full line EDA supplier

Products
Power Compiler reduces power consumption at the RTL and gate level. Power Compiler performs automatic clock gating to reduce the power consumption. With power intent defined by UPF (Unified Power Intent), it inserts power management cells such as isolation, level-shifter, retention registers, power gates and always-on cells as needed.
Talus Power Pro provides RTL-to-GDSII power optimization and management. Talus Power Pro enables optimal power management throughout the flow with power-aware synthesis, physical optimization, clock tree synthesis and routing, allowing designers to minimize power and ensure uniform power distribution.
Primetime PX - analyze the effectiveness of low power design techniques such as clock gating, use of multi-voltage rails and power gating.

Website: http://www.synopsys.com/home.aspx

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This posting is part of the EDA Designline power series and is archived and updated. The root is accessible here. Please send me any updates, additions, references, white papers or other materials that should be associated with this posting. Thank you for making this a success - Brian Bailey.