Synopsys, Inc. has released IC Compiler 2012.06, a part of the Galaxy Implementation Platform. New capabilities include optimizations that can boost operating clock speeds, expanded support for highly fragmented floorplans and new technologies that address advanced process effects.
The release contains several new technologies geared towards boosting design frequency. Clock distribution using a mesh structure has been a staple of high performance designs to minimize variation. However, mesh flows are complex and require expert user knowledge to manage power efficiently. Multisource clock tree synthesis (CTS) leverages automated clock tree and mesh techniques to provide better variation tolerance than traditional CTS, while consuming less power than a mesh.
Processor designers favor the performance scalability and smaller device geometries offered at lower process nodes. In this release, new algorithms leverage advanced process effects to improve timing, reduce buffer count and create more robust circuits for reduced variability. With shorter time-to-market windows and the need for a more integrated feature set, designs are seeing increasing intellectual property (IP) reuse. IP-dominated designs often have highly fragmented floorplans characterized by narrow channels between blocks and a large number of macros and pipelined registers. The latest IC Compiler release can improve timing and routability for such designs.
Transparent interface optimization technology has been improved to provide better timing and faster time to results. In-Design physical verification enables power network verification and improved runtime for foundry-required metal fill insertion.
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