Product Brief
Fairchild uses DesignWare USB 2.0 nanoPHY IP for OTG transceiver
Anne-Francoise Pele3/31/2011 11:19 AM EDT
Fairchild Semiconductor Inc. claimed it has achieved first-pass silicon success for its FUSB2500 UTMI+ Low-Pin Interface (ULPI) USB On-The-Go (OTG) transceiver chip with Synopsys' DesignWare USB 2.0 nanoPHY IP.
Aimed at the high-end handset market, the Fairchild FUSB2500 USB 2.0 OTG transceiver chip was an extremely complex design that would be their first 130nm chip to be integrated by a major manufacturer. Fairchild said it acquired USB IP from Synopsys to be able to focus on the product differentiation and meet the 14 month project schedule.
The Synopsys DesignWare USB 2.0 nanoPHY provides designers with a complete Physical Layer (PHY) IP solution, designed for low power mobile and consumer applications.
Main features:
. Designed for advanced manufacturing processes, the USB 2.0 nanoPHY is targeted to leading 40nm, 45nm, 65nm, 90nm, and 130nm low power (LP) CMOS digital logic processes.
. Integrates high-speed mixed-signal, custom CMOS circuitry designed to the UTMI+ Level 3 Specification.
. Supports the USB 2.0 480-Mbps protocol and data rate (hi-speed).
. Backward compatible to the USB 1.1 legacy protocol at 1.5-Mbps (low-speed) and 12-Mbps (full-speed).
. Can be connected with a Hi-Speed and OTG subsystem to perform as a standard Hi-Speed, Dual-Role Device (DRD), operating as either a fully USB 2.0 Hi-Speed compliant peripheral or an OTG host.
To access the Synopsys DesignWare USB 2.0 nanoPHY datasheet, click here.
Aimed at the high-end handset market, the Fairchild FUSB2500 USB 2.0 OTG transceiver chip was an extremely complex design that would be their first 130nm chip to be integrated by a major manufacturer. Fairchild said it acquired USB IP from Synopsys to be able to focus on the product differentiation and meet the 14 month project schedule.
The Synopsys DesignWare USB 2.0 nanoPHY provides designers with a complete Physical Layer (PHY) IP solution, designed for low power mobile and consumer applications.
Main features:
. Designed for advanced manufacturing processes, the USB 2.0 nanoPHY is targeted to leading 40nm, 45nm, 65nm, 90nm, and 130nm low power (LP) CMOS digital logic processes.
. Integrates high-speed mixed-signal, custom CMOS circuitry designed to the UTMI+ Level 3 Specification.
. Supports the USB 2.0 480-Mbps protocol and data rate (hi-speed).
. Backward compatible to the USB 1.1 legacy protocol at 1.5-Mbps (low-speed) and 12-Mbps (full-speed).
. Can be connected with a Hi-Speed and OTG subsystem to perform as a standard Hi-Speed, Dual-Role Device (DRD), operating as either a fully USB 2.0 Hi-Speed compliant peripheral or an OTG host.
To access the Synopsys DesignWare USB 2.0 nanoPHY datasheet, click here.
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