Soft errors are caused by alpha particles, terrestrial cosmic rays and thermal neutrons that spontaneously flip bits of stored data in a memory or logic chip, resulting in system crashes and network failure. At various altitudes and rates, cosmic rays can corrupt data within a chip, leading to overall electronic malfunctions. Awareness of soft errors can play a substantial role in memory chip invention and production.

The SER problem first gained widespread attention as a memory data issue in the late 1970s, when DRAMs began to show signs of random failures. As process technologies have continued to shrink, the critical charge required to cause a soft error has stayed relatively constant while the charge collection area in memory cells has decreased much faster. As a result, more mitigation techniques are required to ensure acceptable soft error rate levels, particularly in large systems, where the use of memory devices is steadily increasing. The first to market with 90nm-scale devices, Cypress has taken the lead in collecting and testing data about this random phenomenon, locating the sources of SER and creating effective solutions to diminish the wide-ranging problem. Solutions proposed in the book include manufacturing process changes, circuit hardening, design redundancies and system-level modifications.

About the Authors

James. F. Ziegler holds bachelors, masters and Ph.D. degrees in physics from Yale University. Mr. Ziegler worked at IBM for more than 30 years before joining the U.S. Naval Academy in Annapolis, MD, where he currently teaches science to electrical engineers. His 1979 paper suggesting that cosmic rays were a substantial contributor to electronic reliability has become the benchmark in the analysis of system reliability of terrestrial electronics. Dr. Ziegler is a fellow of the IEEE and the American Physical Society. He is the author or editor of 18 scientific books and a myriad of technical articles. He holds 16 U.S. patents.

Helmut Puchner earned his Ph.D. degree in Electrical Engineering from the Technical University of Vienna, Austria. He joined Cypress in 2002 where he now leads a team responsible for transistor development, device reliability, simulation, and compact modeling. His research on SER over the past seven years has resulted in promising soft error mitigation techniques for CMOS technologies. Dr. Puchner is a senior member of the IEEE and has published more than 40 papers and holds 17 U.S. patents.

Distribution and Availability

"SER"History, Trends, and Challenges: A Guide for Designing with Memory ICs" is available today and priced starting at $25 per book. To purchase your copy, visit www.cypress.com/support and click on "Online Store." Other books published by Cypress include "Perfect Timing: A Design Guide for Clock Generation and Distribution" and "The VHDL Programmable Logic Textbook." eeProductCenter's Jon Gabay Says;
Semiconductors are inherently reliable. The tight controls during manufacturing, the refined processes, the rigorous testing and verification all result in a pretty impressive array of reliable devices.

But, our 'id' knows that devices fail. Even with the best of our abilities, many things can and do go wrong. These can be slight impurities, manufacturing defects, over stresses, or, can stem from external forces.

Sometimes, you can do everything right, and still fail. Soft error is one of those failure modes that will glitch an otherwise perfectly functioning part.

Soft errors are caused by nuclear particles. These can tunnel in from the sun or space, or be part of the earth's low intensity background radiation from tiny traces of radioactive elements that occur in all materials. By themselves the particles are generally not dangerous, but they can potentially disrupt the operation of silicon chips and the electronic equipment that depends on them.

Inside a chips, flip flops are at risk from this culprit. A nuclear particle such as a neutron or an alpha particle passing through the silicon can change the charge stored on a nearby transistor. Changes to the charge caused by the ionizing particle are the root cause of a "soft error". Soft because the chip is not physically damaged but may temporarily contain corrupted data.

This is particularly tricky because the soft error may cause the device to temporarily malfunction, even though subsequent testing will show a perfectly working device.

Note, while static registers (mode/control/status/data path etc.) are at risk, SRAM has the likelihood of bearing the most hits from ionizing particles. The sheer number of memory cells in an SRAM make it more of a target.

Exacerbating this problem is Moore's Law. Each new generation of silicon-chip technology, developed about every 18 to 24 months, halves the size of the transistors, making the new chips faster, smaller, and cheaper. But, here's the gotcha. The smaller the transistors are made, the more susceptible they become to the effects of stray ionizing particles. On top of this, the size of embedded SRAM arrays in chips is also increasing exponentially. Presently, embedded SRAM accounts for over 50% of the transistors in a typical chip. The ITRS (International Technology Roadmap for Semiconductors), speculates that this percentage is expected to reach 90% by the end of the decade.

That's why many who share these concerns will welcome what Cypress calls, the 'Industry's First Reference Book on Managing Soft Error Rate in SRAM Design. Called "SER History, Trends, and Challenges: A Guide for Designing with Memory ICs', it addresses process techniques that improve SER immunity, including substrate optimization and techniques to increase node capacitance. (Note, increasing node capacitance is but one technique, and like everything else in life it is a tradeoff. Increased node capacitance may help make a node more immune to soft error, but, it can also slow down the attainable performance).

Many semi makers are addressing this issue with clever and innovative approaches. But, a clear understanding of the problem is always helpful, and this book should be a prerequisite on that path.