Cadence introduces LPDDR3 memory IP solution

A new version of design intellectual property (IP) for the LPDDR3 mobile memory standard includes an integrated controller and PHY support, virtual prototyping, verification IP, and Allegro design-in kits to accelerate implementation and reduce design risk. Designed to provide the high-bandwidth, low-power-consumption performance required by smart phones and tablets, the design IP allows the LPDDR3 standard to be combined with others in a single controller and PHY to enable systems-on-chip (SoCs) supporting multiple memory standards.

In addition, Cadence has upgraded its bandwidth management engine, Placement Queue 2.2, to optimize the way memory is accessed to improve overall system performance and power consumption. For more information about the company’s verification IP catalog and the Allegro Design-in kits, visit www.cadence.com.