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French startup offers compact 32-bit RISC

Peter Clarke
2/27/2006 11:22 AM EST
LONDON — A French startup company, Cortus SA, has developed a highly compact 32-bit RISC processor for embedded applications which it has begun offering for license.

The company, with R&D in Montpellier, France and an office in Redwood City, California, also offers IP around its processor core for applications in consumer, automotive and chip card applications including image processing acceleration and cryptography.

The company, founded in 2005 and which changed its name from Advanced Processing Solutions to Cortus, claimed on its website that it can not only produce small and power efficient cores, but that they can also support out of order instruction completion; something associated with much larger PC microprocessors. According to an entry at the Design & Reuse website semiconductor intellectual property catalog the APS32 requires only 7,000 gates and consumes 18-microwatts per megahertz.

The APS2 has 32-bit fixed-length instructions and there is a set of peripherals including; UARTs, memory interfaces, cache memory controller, configurable interrupt controller, general purpose I/O. AMBA AHB and APB on-chip bus wrappers are in development the company said.

It is not clear whether the design has been taken to silicon but the datasheet shows it benchmarked with Actel and Xilinx FPGAs and in 0.13-micron CMOS from TSMC using Artisan libraries for implementation. In the last case the APS2 core should occupy 0.07 square millimeters and operate at up 330-MHz clock frequency.

“The CPU itself is no bigger than the 8-bit CPU core in a 8051 or a 6811 microcontroller,” the company said. The core is suitable for implementation within a field programmable gate array and the company is a member of an Actel partnership program.

Cortus supplies a free port of the GNU C and C++ compiler and toolchain. The toolchain runs on Linux, Windows XP and most Unix varieties, the company said.

The company is also working on the APS3, optimized for compact code, with a 16-bit instruction format as well as 32-bit long instructions, according to the datasheet.

Related articles:

Royalty-free XAP RISC processor moves to 32-bits

ARM clockless core cuts power to about a third

IP library targets low-cost wireless apps





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