The fourth generation DSP race for base station and front-end Telecom/Datacom processing is about to get tougher. Lucent has stepped onto the track with its new DSP chip architecture, StarPro. Delivering some 3600 peak MMACs at 300-MHz, the StarPro is at the leading performance edge of the DSP pack. And it delivers this performance at a minimal 1.5-W, giving it a large power/MIPS advantage for deployed wireless and Telecom infrastructure.

This is the first DSP with multiple fourth generation DSPs on a single chip. And these are not low-end DSPs; the StarCore DSP can stand on its own as a high-performance fourth generation DSP. By putting three of these DSPs on a chip, Lucent has moved into a new level or processing performance and complexity. The MP DSP chip is supported by ENEA's OSE RTOS, specially tailored for the StarPro's DSP MP operation.

Aimed at the wireless, Telecom, and Datacom markets, the StarPro is designed to handle front-end infrastructure tasks. It has the processing horsepower and the on-chip peripherals needed for a wide range of voice/data applications—wireless or wireline. For example, according to Lucent, the StarPro can handle voice/data applications including supporting 64 Full Rate ADSL channels, or processing 64 wideband CDMA base station wireless voice/data channels, or the speech coding and echo cancellation for 64 wireless voice channels. Three on-chip Serial I/O Units (SIU) support high-speed TDM and packet data flow, including T1/E1 connections. Each SIU provides a full-duplex, double-buffered, serial port with programmable I/O frame and bit clock control.

System-On-Chip
But what makes StarPro truly unique is its system-on-chip approach. It is not just a DSP engine, it is truly a system on a chip with three StarCore DSP processors, main memory, and peripherals. These elements are tied together with an on-chip systems bus, the Daytona Bus. This architecture is built like a system-on-chip. It is not a fixed, proprietary IC, but is designed to be internally scalable and extensible, as a good SoC is. Lucent is offering this as a chip, but it incorporates a good deal of the company's expertise as one of the leading ASIC houses.

There has been a lot of talk about system-on-chip technology, but most SoCs are really implementations of a processor integrated with its on-chip memory and peripherals. Most SoCs use a processor bus or some variation of a processor bus as the SoC main bus. Thus, most SoCs are processor-centric, tied to a central or perhaps distributed processor-related bus.

StarPro is a different affair. It is built around two major architectural elements—the StarCore DSP architecture and the Daytona systems bus. The DSPs provide the processing horsepower and the Daytona bus provides the high-performance system inter-chip connection. And this is a true systems integration, for the Daytona bus is not a processor bus. Instead, it's more a VME or CompactPCI systems bus that treats all system elements on the chip as bus elements, without one dominating bus operations. These bus elements include the StarCore Macrocell (DSP core, 8-KB I and D caches, and 16-KB local memory), Serial Interface Units (SIUs), a Parallel Interface Unit (PIU), two 32-bit External Memory Interface Units (MIU), and main memory (768-KB).

Daytona Bus
The key to this MP DSP chip is its on-chip system bus, the Daytona bus. This bus was designed to support multiple bus devices, including DSP processors, with a minimum of overhead. Moreover, it was tailored to provide an efficient pathway between devices for short and even single cycle transactions. Because it's a wide bus, 128-bits, it can move a lot of data in one cycle. And by optimizing short burst transactions, the bus minimizes burst latencies and provides bus resources on almost a cycle by cycle basis to the bus devices, including the DSPs.

This is a wide, on-chip, synchronous split-transaction system bus that was developed by Bell Labs, Lucent's R&D arm. Daytona runs at the DSP's clock rate, 300-MHz, and is designed for MP operations. It relies on a central arbiter to prioritize and select the transactions to run. It is a non-multiplexed bus, with separate address bus and data bus. Also, Daytona is a generalized bus and supports heterogeneous processors ranging from DSPs, uPs to ASICs, and memory. All devices have IDs, these are used to identify local memory spaces and for arbitration. All transactions have an ID as well (Initiator ID + a sequence #).

By implementing split-transactions, the bus can separate the transaction request (command and address) from the data transaction. Transaction requests can be made for the address bus, with the data transaction carried out later by the target on the data bus. This split-transaction approach enables bus-inefficient Reads to be converted into target Writes (host Read request goes to the target, which converts it into a target-to-host Write).

The Daytona bus is 128-bits, or eight 16-bit words, wide. Running at 300-MHz it can deliver 4.8 Gigabytes of peak bandwidth. Moreover this is an SoC systems bus. It is designed for SoC systems operation, not for long burst, board-type systems. Thus the bus can accommodate short burst accesses or even single cycle accesses with very high efficiencies. Because it's on-chip, unlike board system buses, it can be very wide—128-bits. And thus it can move a lot of data on a single cycle, providing enough 16-bit instructions for almost three DSP instruction fetch cycles in a single Daytona bus cycle.

StarCore
StarPro builds on the VLIW DSP architecture that Lucent and Motorola jointly developed in the StarCore organization. The resultant DSP processor, the StarCore, combines high performance with low power dissipation. StarCore is a six-issue VLIW, with four ALU/MAC/Shift functional units and two addressing units. Running at 300-MHz, the DSP delivers a peak 1200 MMACs (300-MHz x four MAC units). This is a fourth generation architecture, one that is competitive with Texas Instruments C6x VLIW, an eight-issue machine at 300-MHz (and going to a GHz), and Analog Devices' yet to be released TigerSHARC, a VLIW/SIMD DSP.

StarCore is a very innovative architecture. It is a VLIW, one that can issue up to six 16-bit instructions per cycle. But this is not a fixed-VLIW implementation with six fixed instructions per fetch block. Instead, the StarCore takes on some of the characteristics of the 68K: it has extensible instructions, with potentially multiple 16-bit words for an instruction. Additionally, the fetch set of instructions is also extensible.

Release and Pricing
StarPro is a high performance fourth generation DSP, but it is priced very competitively. The starting price will be $100 (100,000). The chip will be sampling by the end of the year, with production in the first or second quarter of 2001.