The fact that electronic systems designers are under intense time-to-market pressures is now accepted as a basic fact in the industry. Many hardware and software companies like to tout their products as helping engineers meet this challenge. The entire programmable logic industry was created to address that issue. However, engineers today face a new set of time-based challenges and the old solutions aren't keeping up.

The first of these new challenges is called "time to volume." Designers today must not only create advanced functionality, but also make sure they can create systems that can be quickly and efficiently delivered in the volumes needed to meet consumer demands. Nowhere is this factor more important than in telecommunications and data communications where the insatiable demand for more bandwidth is making a lot of people wealthy and depriving a lot of engineers of badly needed sleep. The second challenge can be labeled "time to margin." Product shelf life is shrinking and that means profitability must come earlier and at lower volumes. This requires engineers and design managers to consider the bottom line at every stage—not just in the design phase of product development.

Programmable logic traditionalists continue to try to adapt their older products to deal with these pressures. This is illustrated by the strong support given to semiconductor intellectual property (IP). Reliance on soft IP to deal with time issues was a major innovation that solves many problems, but can be problematical. For instance, using IP in traditional programmable logic means added time for optimization and requires a much larger device. This affects all three time challenges. Rapid migration to smaller process technologies helps hold down costs but doesn't necessarily enable faster time to volume. Tweaking old ideas doesn't necessarily provide effective relief for 21st century design headaches.

The ideal solution to the growing list of time-based engineering challenges is new hardware that gives engineers the flexibility they need combined with the economics and performance efficiencies of standard products. At QuickLogic, we call the category embedded standard products (ESPs). Some analysts refer to it as application specific programmable products (ASPPs), where these devices are comprised of embedded functions and efficient programmable logic connected by a high-speed interface on a single silicon chip.

While the potential applications for ASPPs is almost unlimited, most designers focus on low-power, high-performance applications such as PCI, DSP, and RAM. Recently, one embedded processor designer announced an alliance to add two of its microprocessors to the lineup of applications. This creates the possibility of a system-chip with all the flexibility of programmable logic added in.

ASPPs are not some kind of hybrid chip. They are distinctly different from traditional programmable-logic solutions. First, the functionality is embedded and optimized for a specific architecture. This dramatically increases performance (some QuickLogic devices run at greater than 600 MHz internally), as well as reduces overall die size. Embedded functionality frees engineering departments from having to add layers of expertise in specific applications. This is particularly important in areas such as DSP where there simply isn't enough expertise to go around. In addition, because functionality is embedded, designers know they can go directly to the manufacturer for support rather than being passed along to third-party suppliers of soft cores.

A number of analysts take this new category seriously and see great potential for it. Dataquest notes that ASPPs can address both leading-edge and mainstream OEMs by cutting time factors, offering a software development platform, and leveraging engineering resources. A Dataquest report noted that ASPPs are "generally a superior solution" to traditional programmable logic.

ASPPs are not the ultimate solution for all challenges. Putting a soft core into an FPGA or CPLD can work for a number of applications in low-volume systems that are cost-tolerant and demand less performance. For low-volume systems, ASICs remain the solution of choice. However, neither of these solutions offers the potential for both flexibility and performance that ASPPs give to designers.

What it really comes down to is that new design challenges call for solutions that go beyond an edited version of the past. Faced with rapidly escalating time pressures, designers and OEMs need new thinking and new approaches. ASPPs are far more than a modified version of an older solution and offer the kind of alternative that will move the industry forward.

Tom Hart, a 30-year semiconductor industry veteran, has served as president and CEO of QuickLogic since June 1994. Hart has held senior management positions at major electronics companies including National Semiconductor, Motorola, and Silicon General. He holds a B.S.E.E. from the University of Washington.