Product Brief
DSP removes programming barriers for parallel processors
Ismini Scouras2/14/2007 3:08 PM EST
Based on the company's SPI Stream Processor Architecture, the Storm-1 family combines the ability to scale to 80 giga multiplications and accumulations per second (GMACs/s) performance with a C programming model. The chips are housed in a 31x31mm plastic ball grid array (PBGA) packaging and implemented in 130-nm, 1-V standard CMOS process. For more on the architecture, go to www.streamprocessors.com/streamprocessors/Home/Technology.html.
The Storm-1 family is suitable for a wide range of demanding signal processing applications, such as high-definition video H.264 HD encoding, transcoding, analytics, image processing and video surveillance with processing headroom for customer-specific enhancements.
The Storm-1 SP16-G160 device is a DSP that offers 160-giga operations per second (GOPS) and 80-GMACs/s of performance by featuring a high-performance data-parallel unit (DPU) with 16 parallel lanes with five ALUs each. Each ALU contains a MAC unit and is capable of four 8-, two 16- or one 32-bit operation per cycle. Input and output data for each lane is stored in on-chip lane register files that are allocated by the compiler to maximize data bandwidth.
Each device includes a MIPS32 4KEc CPU core for system tasks, and a second MIPS32 4KEc that is dedicated to handling main DSP threads and making kernel function calls to the DPU for acceleration. A rich set of I/O includes Gigabit Ethernet, PCI, and high-speed data ports for video and communications.
Pricing: $99 for the SP16-G160 and $59 for the SP8-G80 in 10,000-unit quantities.
Availability: Sampling with full production expected in the second quarter of 2007.
White Paper on stream processing: click here.
Stream Processors Inc., +1 (408) 616 3338, www.streamprocessors.com.



