Stretch unveils second-generation software configurable processor architecture

Stretch Inc. announced its S6 Software Configurable Processor (SCP) architecture. Optimized specifically for high-performance video and wireless signal processing, the S6 Architecture offers unmatched price/performance in these demanding applications. At the heart of the new architecture are three technology innovations: the second-generation Instruction Set Extension Fabric (ISEF), the Processor Array, and the Programmable Accelerator. The combination of these advancements provides unprecedented single-chip compute power and the ability to easily scale to multi-chip implementations for the most compute-intensive applications.

Craig Lytle, President and CEO said, "We are very excited about the new S6 Architecture. The S6000 family of devices will revolutionize the way in which people think of high performance signal processing solutions. Building on our experience with our groundbreaking S5 family of devices, and working very closely with our customers, we created a new architecture that delivers a price/performance point second to none in the industry."

The S6 Architecture enables previously unattainable, single-chip implementations of applications such as H.264 High Definition encoding. A single S6000 family device can perform 4 channels of 4CIF/D1 H.264 BP encoding at 30fps or 16 channels of CIF resolution at 30fps, enabling H.264 encoding at less than $1.60/channel. The S6 SCP Engine has Stretch's second generation Instruction Set Extension Fabric (ISEF) embedded directly within the Tensilica Xtensa LX dual-issue VLIW Processor architecture.

The ISEF is a software configurable compute fabric that enables system designers to extend the processor instruction set and to define new instructions using C/C++ code. These "extension instructions" are then automatically synthesized, placed, and routed into the ISEF. Stretch has made several key improvements to the ISEF for the S6 architecture family, resulting in improved performance and reduced die area. In addition to enhancements to the compute elements in the ISEF, 64KB of distributed ISEF RAM (IRAM) has been added to allow for the storage of data within the ISEF itself. To support the enhanced processing capabilities of the architecture, a dedicated high speed DMA channel has been added to ensure that data is always available.

Optimization of the ISEF compute elements and routing structures provide 300MHz operation, three times the performance of the original architecture. The new ISEF fabric can be dynamically reconfigured in less than thirty micro seconds, four times faster than the original fabric.

The increasing complexity and diversity of video and wireless standards are driving companies to create scalable systems with varying degrees of processing power, depending upon the application requirements. To enable its customers to easily create systems of varying compute levels, Stretch developed the Processor Array solution. At the physical layer, each S6 device can interface with up to 4 other processors through dedicated 1.2GB/S DDR interface banks, allowing system architects to create processor topologies best suited for their application. So that the processor is not burdened with Processor Array functions, each S6 device has a dedicated processor network interface and switch circuitry to accommodate inter-processor communication. At the software layer, programmers can dedicate tasks, establish communication channels between processors, and even share resources between processors using a rich library of BIOS calls or custom-created C/C++ code.

The first member of the S6000 Family, the S6105, will be available in the third quarter of 2007. Unit pricing for 50K S6105 is set at $25 in 2008.