Figure 1. The DRPIC166X soft IP core offers 4x performance of the standard architecture.
Digital Core Design (DCD) has announced the DRPIC166X - a fully static soft IP 8-bit core that is software compatible with PIC16XXX MCUs while delivering 4x faster performance compared to the standard PIC16XXX architecture (Figure 1).
The core consumes just 37 uW/MHz in 0.18u technology and achieves a 1.3 GHz virtual clock frequency in a 0.18u technological process or 800 MHz virtual clock frequency in a 0.35u technology.
The DRPIC166X MCU core is intended for applications including high-speed automotive and appliance motor control, low-power remote transmitters/receivers, pointing devices, telecom processors or consumer electronics. With its built-in power save mode, the IP core is well suited to power-sensitive applications.
Figure 2. The DRPIC166X soft IP core combines an enhanced Harvard architecture with multiple peripherals.
Key features of the DRPIC166X MCU soft IP core (Figure 2) include:
- 35 instructions
- 14 bit wide instruction word
- Up to 32K bytes of Data Memory
- Up to 64K bytes of Program Memory
- Configurable hardware stack
- Power saving SLEEP mode
- DoCD debug unit offering processor execution control, read-write for all processor contents, and hardware execution breakpoints
- Fully synthesizable, static synchronous design with no internal tri-states
- Technology independent HDL Source Code
- Four 8 bit I/O ports
- Timer 0 - 8-bit timer/counter
- Timer 1 - 16-bit timer/counter
- Timer 2 - 8-bit timer with prescaler
- Watchdog Timer
- Interrupt Controller
- Optional peripherals include SPI and I2C master and slave bus controllers
Designed to operate with on-chip dual ported memory, the new core implements a pipelined Harvard RISC architecture - offering separate instruction and data memories with independent address and data buses. With this enhanced Harvard architecture, instruction fetch and data operations can occur simultaneously using the 14-bit program memory and 8-bit dual-port data memory. As a result, the multi-state pipeline can overlap instruction fetch and memory transfers so that the next instruction can be fetched from program memory while the current instruction is executed using data from data memory.
The architecture ensures that most instructions are executed within one system clock period, except the instructions such as GOTO, CALL, and RETURN, which directly operate on the MCU PC (program counter). In this case, one additional clock cycle is required to clear and subsequently refill the pipeline.
DCD delivers the DRPIC166X core with a fully automated testbench comprising a complete set of tests and DCD's DoCD Hardware Debug System - a real-time hardware debugger that provides debugging capability of a complete SoC.
The DRPIC166X MCU soft IP core is available now in HDL source format (VHDL, Verilog RTL synthesizable source code) and netlist format (EDIF/NGO/NGD/QXP/VQM). DCD offers the core with single-site and multi-site licensing options without royalty-per-chip fees.
For more information, visit www.dcd.pl/ipcore/82/drpic166x