In addition to low jitter, ADI's clock ICs improve system performance through the integration of several key functions that eliminate the need for multiple discrete components, reduce board space, and ultimately reduce BOM (bill of materials) costs. These features include a low-phase-noise PLL (phase locked loop) frequency synthesizer core, programmable dividers, and adjustable delay blocks. Combined with sub-picosecond jitter performance, these features make ADI's clock ICs the industry's best at maximizing the performance of critical-signal-path components, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), direct digital synthesizers (DDSs) and mixed-signal front end (MxFE) devices.

"As the industry leader in data conversion, ADI continually seeks to provide customers with the highest levels of system performance, and ADI's clock ICs are key to improved system performance," said Kevin Kattmann, product line director, High-Speed Converters, Analog Devices. "As frequencies and data rates move higher and higher, the accuracy of a system and the performance of its converters is increasingly limited by the quality of the clock signal. ADI's new series of clock ICs combines best-in-class signal integrity with innovative functionality, allowing customers to achieve optimum system performance, while greatly simplifying the clock tree design task."

ADI's clock IC offerings include both clock distribution and clock generation devices.

ADI's Clock Distribution ICs — AD9510, AD9511, and AD9512

ADI's clock distribution IC series includes the AD9510, AD9511, and AD9512. These devices feature sub-picosecond performance over a broad frequency range, higher levels of integration and more programmability than other solutions.

• Low-phase-noise Clock Outputs with Sub-Picosecond Jitter
  Low phase noise and low jitter are key to reducing overall noise in a signal path. ADI's clock distribution ICs feature LVPECL outputs, as well as user-selectable LVDS and CMOS options:
• LVPECL outputs operate to 800 MHz with additive jitter less than 250 fs (femtoseconds) rms.
  
• LVDS and CMOS outputs operate up to 800 MHz and 250 MHz, respectively.
  
• In both LVDS and CMOS modes, the additive jitter is less than 300 fs rms.
  

  The voltage levels for both LVPECL and LVDS clock outputs are programmable, allowing the system designer to determine the best voltage swing for a given application. The AD9510 offers the most flexibility, mixing LVPECL, LVDS and CMOS logic for a total of eight independent clock outputs. For designs requiring fewer outputs, the AD9511 and AD9512 pack five independent outputs into a smaller package at reduced power consumption.
  

• Programmable Dividers
  ADI's clock distribution ICs eliminate the extra components required to generate gate delays and phase shifts, by using dividers with dramatically increased functionality. Each clock divider is programmable to any integer ratio from 1 to 32, offering flexibility when handling multiple frequencies on one PCB (printed circuit board). The divide function also includes a user-selectable offset word that enables channel-to-channel phase control. Because the devices perform phase control inside the divider block, they maintain much lower jitter than equivalent discrete implementations.
  

• Programmable Delay
  ADI's clock distribution ICs feature on-chip programmable delay allowing users to adjust for set-up and hold-time requirements between data converters and digital ASICs, FPGAs (field-programmable gate arrays), and digital up/down-converters, without adding extra clock hardware. All three AD951x products include at least one fine-delay-adjust channel with a programmable full-scale range from 1 ns to 10 ns. A 6-bit delay word offers 64 unique delay settings with step sizes as low as 16 ps.
  

• Integrated PLL Frequency Synthesizer Core
  Both the AD9510 and the AD9511 integrate a low-phase-noise, 1.5 GHz PLL frequency synthesizer core on chip. The PLL is optimized for clock applications and consists of a programmable reference divider, a low-noise phase frequency detector, a precision charge pump, and a programmable feedback divider. For applications that do not require an on-chip PLL, the AD9512 offers two 1.5 GHz clock inputs and five independent clock outputs.
  

Availability and Pricing

The AD9510 is sampling now with production quantities available in February 2005. The AD9511 and AD9512 begin sampling in December 2004 with production quantities available in March 2005. The AD9510 is offered in 64-lead LFCSP (lead frame chip scale package) and is priced at $11.95 per unit in 1,000-piece quantities. All three AD951x products are specified to operate over the extended industrial range of -40C to +85C. For more information, please visit ADI's website.

ADI's Clock Generator IC — AD9540

In addition to clock distribution, ADI also supports clock generation with the AD9540, released earlier this year. Specifically designed to support the stringent clocking requirements of high performance data converters, the AD9540 clock generator helps reduce system cost and provides valuable flexibility. The AD9540 features high-performance PLL circuitry, including a flexible 200 MHz phase frequency detector and a digitally programmable charge pump current. The device also provides a low-jitter (less than 700 fs rms), 655 MHz CML mode (PECL compliant) output driver with programmable slew rates. External VCO (voltage-controlled oscillator) rates up to 2.7 GHz are supported. Extremely fine frequency tuning resolution (48-bit tuning word) and 14-bit phase adjustment enable ultra precise control of the output's phase and frequency. The AD9540 is specified to operate over the extended industrial range of -40C to +85C.

Availability and Pricing

The AD9540 is available in full production and is offered in a 48-lead LFCSP. It is priced at $9.95 per unit in 1,000-piece quantities. For more information, please visit: www.analog.com/AD9540.

Steve Ohr has these observations
Clock generator ICs seem to be getting a lot of attention these days. Lattice Semiconductor introduced a part with programmable skew control on eeProductCenter during the summer, and generated a high number of clicks. Similarly, Agere Systems generated an article of system-level timing for Planet Analog, and it too generated enough page views to be considered one of the favorite online articles of 2004, and will be subsequently re-printed in the December Planet Analog magazine folio.

Clock trees can be a complex undertaking, these authors profess; even small amounts of jitter or phase shift can propagate false logic triggers and throw system timing way out of whack. It takes real analog expertise to keep these phase shifts under control. Analog Devices' entry into the business is auspicious and welcome.

"High-performance clocks are critical to signal processing applications," confirmed Scott Behrhorst, Analog Devices' Designated Hitter (their Clock Marketing Manager). But his concerns go beyond boards and card cages. In wireless infrastructure radios (cellular basestations), he points out, noise on clock line result in higher Bit Error Rate (BER), and poor call quality. Spurious signals on the clock lines can result in Adjacent Channel Interference (ACI) and dropped calls.

Within test and measurement applications, noise on the clock line degrades the user's ability to make accurate measurements. Clock noise will also degrade images in medical equipment, increasing the chance of a false diagnosis.

Larger than you think

Though not as glamorous as digital signal processors (DSP) or data converters, clock generators and clock distribution devices contribute to an increasingly hefty market segment. Clock generation ICs amounted to $934 million in 2003 and will likely growing to roughly $2 billion by 2008, according to market tracker DataBeans (Reno, Nev.) If you add real-time clocks and timers to the picture, Databeans says, the total available market (TAM) was over $1 billion last year and even larger today. Its CAGR is something like 16 percent.

ADI's acknowledged competitors include Integrated Circuit Systems (which has an extremely large footprint here), as well as Cypress Semiconductor and IDT. ADI's market entry positioning claims that

• Existing suppliers do not offer cost effective solutions for the most demanding, high performance clock requirements
  
• No supplier adequately specifies and tests products for clocking data converters
  
• When jitter numbers are provided by suppliers, they are given over a limited bandwidth
  
• Few products with sub-picosecond jitter offer high integration. The exceptions tend to be highly application specific products not useful across broad markets
  

What ADI brings to the party is a series of parts said to keep clock jitter down to less than 1 picosecond. There were two part types announced at the end of November: The AD9510 and the AD9540.

The AD9510 (and its AD9511 and AD9512 variations) is a multiple-output clock distribution IC featuring sub-picosecond stability over a broad frequency range. These devices provide higher levels of integration and more programmability than existing solutions, ADI claims.

Specifically, the AD9510 has a 1.5 GHz PLL core and puts out 8 clock signals dividable from 800MHz. There are four LVPECL outputs spec'd with 225 fs rms jitter (from 10kHz-350MHz), and four LVDS/CMOS outputs spec'd for 275 fs rms jitter (10kHz-350MHz). Each channel is separately programmable: Its frequency can be divided by any integer from 1-32; its channel-to-channel delays and phase offsets can be similarly controlled. Two channels offer programmable delays from 1 to 10ns. The on-chip PLL can be similarly adjusted for setup and hold. Samples are available now and production release will occur in February or March.

The AD9540 is more of a building block, designed to reduce system cost and provide flexibility. It uses a high-performance PLL, with a flexible phase frequency detector and a digitally programmable charge pump.

The AD9540 will clock data converters. Its jitter is spec'd at <700 fs rms. Phase noise is less than 135 dBc (with a 1 kHz offset). Its spurious-free dynamic range (SFDR) is -80 dB at 160 MHz (with a 100kHz offset). It offers 8 phase/frequency profile settings, a 200 MHz phase/freq. detector and a 655 MHz CML- or PECL-compliant output. It's in production now.

Visit the AD9510'sProduct Page, which also covers the AD9511 and AD9512... or take a look at the preliminary Data Sheet for the AD9510.