Memory goes multicore

The second downside is that the parallel access overhead of the Ashwood memory architecture slightly slows down memory access times to individual memory cells—a disadvantage that is offset by its many parallel access channels, Ashwood said.

"For instance, if a NAND flash chip has an access time of 20 to 50 nanoseconds today, adding my architecture would increase that access time to 50 to 70 nanoseconds," he said. "But remember, during that time, 100 or more other memory retrieval operations could be in progress concurrently, yielding an effective access time of just a few nanoseconds per retrieval."

Late last year Ashwood filed a patent on his memory architecture, but because chip makers could implement it before the patent is grated, he is choosing to keep most of the architecture secret until the patent is granted next year

"This architecture is so easy to implement—a chip maker could roll out a working prototype in as little as three months," said Ashwood.

Ashwood, however, has disclosed the main outlines of its functions—reorganizing the memory hierarchy for parallel access to a chip's data—as well as described its features and made performance comparisons with both DRAM and hard disks.

"Unlike traditional memory architectures that degrade in performance as more bit cells are added to an array, our memory architecture's performance increases each time you add cells," said Ashwood. "For instance, because of the way our architecture scales, if you double the capacity of our memory chip, it also becomes twice as fast as before."

Overhead is low, too, adding only about 3 percent to the die area of a memory chip, according to Ashwood.

"Current flash cells are already extremely dense—they should be able to fit a terabyte in less than a cubic inch," said Ashwood. "The problem is that their yields would fall to 30 percent and the speed to just 32 million bytes per second. Utilizing my technology with the same flash cells allows a yield in the upper 90 percent [range] and a speed of 16 billion bytes per second."

When using the Ashwood memory architecture with multiple flash chips configured as a solid-state disk (SSD), instead of adding 3 percent, each memory chip's die area could actually be smaller than it is today, because the access circuitry to the SSD would be common to all the memory chips on the drive, he said.

Using his memory architecture will also increase the lifetime of a drive, according to Ashwood. Flash cells can only endure about 100,000 cycles before they burn out. By offering greater flexibility in the page reassignment, he said, the Ashwood memory architecture can increase the lifetime of a drive by about 500 times.