Synopsys announces synthesizable PowerPC cores

Venice, Florida — Synopsys, Inc.has developed fully synthesizable implementations of the IBM PowerPC 460 and cache configurable PowerPC 405 embedded microprocessor cores as components of the DesignWare Star IP program.

The PowerPC 460S is a 32-bit high performance, low-power embedded processor core optimized to meet the performance and power requirements of today's consumer electronics, communications, and storage applications. The PowerPC 460S allows designers to select the L2 cache size, L1 cache size, and multi-core processor local bus necessary to optimize their design. Additionally, the PowerPC 460S supports an optional floating point unit.

The PowerPC 405S is a 32-bit low power, mid performance embedded processor core with design attributes that make it an ideal solution for emerging consumer, storage, wired and wireless applications. The PowerPC 405S supports a user-definable L1 cache size that helps SoC designers optimize performance and area to match the application requirements.

Developed through a close collaboration between IBM and the Synopsys Professional Services and DesignWare IP teams, the foundry-independent processor cores are supported by a broad range of Synopsys design tools. The PowerPC 460S and 405S processors are distributed as simulation and timing models and synthesizable register transfer level (RTL) cores. Synthesizable IBM CoreConnect peripherals are also available to licensees of the PowerPC cores.

Synopsys' distribution of the PowerPC cores supports the goals of Power.org, an open organization that develops and promotes the Power Architecture and its supporting technologies. Synopsys is a founding member of Power.org.

Availability

PowerPC 460S and PowerPC 405S design views, including the simulation and timing models, a verification environment, and full documentation are currently available at no additional charge to DesignWare Library customers. For an additional fee, DesignWare Library users may license from IBM or Synopsys the implementation views of the core, including fully synthesizable RTL.

For more information, visit PowerPC.html.