ARM introduces S/W interface standard for Cortex-M series processors

The folks at ARM have announced the availability of the ARM Cortex Microcontroller Software Interface Standard (CMSIS), a vendor-independent hardware abstraction layer for the Cortex-M processor series. The CMSIS enables consistent and simple software interfaces to the processor for silicon vendors and middleware providers, simplifying software re-use, reducing the learning curve for new microcontroller developers and reducing the time to market for new devices.

Of particular interest to readers of Programmable Logic DesignLine (www.pldesignline.com) is the fact that CMSIS will work for Cortex-M1 and future Cortex M-profile variants, because the Cortex-M1 is designed and optimized for FPGA-based implementation (see this Actel Implementation, for example).

Creation of software is acknowledged as a major cost-factor by the embedded industry. By standardizing the software interfaces across all Cortex silicon vendor products, this cost is significantly reduced, especially when creating projects for new devices or migrating existing software to a Cortex processor-based microcontroller from other silicon vendors.

The creation of the CMSIS enables silicon vendors to focus their resources on the differentiating peripheral features of their product, and eliminates the need to maintain their own individual and incompatible standards for programming a microcontroller.

The CMSIS has been developed in close partnership with several key silicon and software vendors including Atmel, IAR, KEIL, Luminary Micro, Micrium, NXP, SEGGER and STMicroelectronics. This collaboration, together with feedback from previous solutions, has resulted in an easy-to-use and easy-to-learn programming interface for Cortex processor-based devices.

The standard has been designed to be fully scalable to ensure that it is suitable for all Cortex-M processor series microcontrollers from the smallest 8KB device up to devices with sophisticated communication peripherals such as Ethernet or USB-OTG. (The CMSIS memory requirement for the Core Peripheral Access Layer is less the 1KB code, less then 10 bytes RAM).

In the future, ARM plans to extend the CMSIS with a Middleware Access Layer that provides standard software interfaces for Ethernet, SD/MMC, and a debug interface for consistent kernel-aware debugging of RTOS kernels. This extension to the CMSIS will simplify the deployment of standard middleware components on new Cortex processor-based microcontrollers.

Availability
Provided as a set of comprehensive documentation that is designed for integration into device user's guides, the CMSIS is available for free download from www.onARM.com, a website providing a comprehensive resource for embedded developers. CMSIS documentation and maintenance of the software layer will be provided by ARM.