• M8051W is a high performance, 2-cycle implementation of the 8051 architecture
• M8051EW is a debug-enhanced version of the M8051W
• M8051 is the classic 12-cycle implementation the 8051 architecture
• M8052 is an enhanced variant of the M8051 with more memory and a 3rd timer

"The M8051 has been one of our most popular lines of IP with many customers both large and small," says Aaik van der Poel, Mentor Graphics Continuing Engineering Division Business Unit Manager. "IPextreme's deep experience in the IP business and their ability to continue to make this product available will delight our many customers."

Originally part of Mentor Graphics' Inventra IP business, the M8051 is a silicon-proven, synthesizable processor core that is binary compatible to 8051 devices and is available in both VHDL and Verilog formats. IPextreme will package the M8051 cores in its XPack technology to provide support for all major EDA flows, including Mentor Graphics Precision FPGA synthesis tool. In addition, users of the M8051 cores can leverage the immense ecosystem of evaluation systems, development systems, compilers and application software for the 8051 architecture.

Richard Darley, a renowned 8051 architect, says, "The 8051 architecture was developed nearly 30 years ago and continues to win the hearts of engineers for its small footprint and usefulness in a broad range of applications. The 8-bit world is alive and well."

Availability
The Mentor Graphics M8051 cores are available for licensing now. Like all IPextreme IP, the core is offered in a complete package of synthesizable source code, integration test bench, and complete documentation.

For additional product information, please see www.ip-extreme.com/IP/m8051.