Tilera announces plan for 100-core processors

Top Layer uses 64-core chip
SAN JOSE, Calif. — For Mike Paquette and the engineering team at Top Layer Networks, the many-core world is here today. The company is designing a network intrusion detection system using the 64-core processor from startup Tilera Corp. which Monday (Oct. 26) announces plans for a next-gen, 100-core part.

See video of Tilera CEO Omid Tahernia discussing the implications of the company's 100-core processor announcement.

The two companies are among a handful living at the bleeding edge of an emerging many-core era. Analysts and researchers say it could take years--and require major breakthroughs in parallel programming--before the broad computer and embedded industries can follow them.

The transition to parallel software represents the hardest computer science problem in 50 years, said David Patterson, professor of computer science at the University of California, Berkeley and director of a new parallel computing lab there.

Patterson will describe the issues and present a new method for benchmarking many-core processors in a keynote Wednesday (Oct. 28) at the Many-Core Virtual Conference sponsored by EE Times. Top Layer and Tilera will also talk about their experiences at the online event.

Top Layer has an intrusion detection system that can scour packets at rates up to 4.4 Gbits/second using a set of homegrown ASICs and FPGAs. But that wasn't going to cut it for tomorrow's 10 Gbit/s Ethernet networks.

Rather than re-spin all its ASICs and FPGAs, the company started looking for alternatives from fables startups. Today it has a working prototype of its future system that exercises all 64 cores in of Tilera's current high-end processor.

Paquette said his team liked the fact Tilera taps existing Linux tools for symmetric multiprocessing systems, treating its many-core processor like a multi-CPU server. The approach lets Top Layer give a single core many jobs or spread a single job across many cores.

"The hard part was converting our software from the ASIC and FPGA design, nothing specific to the Tilera software which was quite straightforward," said Paquette.