ADI reduces power and cost for its direct digital synthesizers

Traditionally, portable and embedded systems designers looking to add frequency synthesis capability choose to go with phase-locked-loops (PLLs) or implement it on their field-programmable gate arrays (FPGAs). Analog Devices is now adding another choice to the mix with its AD9913 direct digital synthesizer (DDS). This new DDS aims to offer portable and embedded system designers a viable option that compares on cost, power consumption, and performance.

DDS has long been favored in instrumentation (because of fine-tuning capabilities), military/aeronautic (because the ability to sweep frequencies) and secure communication (because of frequency hopping settling time) applications. Embedded designers tend to use FPGAs and then add a digital/analog converter (DAC) to their design to get DDS functionality. To address this market, ADI specifically optimized for low cost: "We are making it possible to get it for the same price as the DAC they would have to buy anyway," says Jeff Keip, ADI's senior product marketing manager. "This cuts down on the amount of signal routing required; now it only requires a couple of lines from the microcontroller instead of routing 10 to 12 signals."

In portable applications, designers tend to use PLLs. To address this market, ADI cut power. "This is the first DDS with a clock rate of 250-MHz while consuming only 50mW," said Keip. How did they do that? DDS requires a translation from angle to amplitude prior to sending the signal to the DAC. Historically, this has been done with a look-up table of sinewave values (as in an FPGA). "That is very power hungry, making it poorly suited for portable applications," explained Keip. ADI's design teams have gone through a number of iterations on a proprietary algorithm to get the job done, and they also bias the device from a +1.8-VDC supply. Finally, the ADI DAC team designed a device focused on low-power consumption.

Key notables include: greater than 80-dB spurious-free dynamic range (SFDR) performance on a 100-MHz output signal, on-chip 10-bit high-speed DAC, fine-tuning granularity (58uHz tuning resolution without deploying an optional programmable modulus function), and for max output frequency of 100 MHz, phase noise is -130 dBc/Hz @ 1 kHz offset.

Housed in a 32-lead LFCSP (lead-frame chip-scale package), the AD9913 is available in full production quantities with a cost of $4.65 per unit in 100,000-unit quantities. Click here for more information.

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