Called Teja FP, Bryon Moyer, VP of Product Marketing at Teja Technologies, claims it is the first and only development platform that enables network OEMs to implement their packet processing designs in software on FPGAs with multiple embedded processors.

Teja FP builds on the company’ existing Teja NP which uses a state-diagram-like methodology to allow a developer to define a complete system's application logic in a C-based, hardware-independent model that is separately mapped to the various resources of the target hardware configuration, resulting in the automatic generation of optimized production code for the target system.

A key feature of Teja NP, and of Teja FP, is the NPOS runtime system, a parallel processing framework with a rich library of system service APIs. To enable hardware and software development of softcores directly on FPGAs, rather than go through an intermediate RTL level code generation step, the company has developed a proprietary compile engine that outputs the design information in a form ready for implementing on the specific FPGA device.

The first implementation of Teja FP is configured for use on the Xilinx Virtex 4 FX flagship family of FPGAs and includes the multi-core infrastructure IP, a rich set of APIs, and productivity tools. Teja is also providing a library of data plane applications in extensible source code.

According to Moyer, Teja FP is designed to allow developers create an entire FPGA-based multicore design, including the hardware architecture, in the widely used C language instead of RTL, and without relying on C-to-RTL conversion. He said Teja FP includes pre-designed multi-processor fabric components plus other IP elements that are easily assembled, configured, and managed through APIs by engineers without a deep knowledge of multi-processing.

Early access to Teja FP is available now, with general availability in Q3 2006.