Infineon
The Lowdown on Low-K: Concept becomes production reality
November 6, 2003; 11 am PT/2 pm ET
Inter-metal capacitance was identified early on as one of the serious challenges to circuit designers working in 130 nm processes. The most promising solution appeared to be finding ways to reduce the dielectric constant, K, of the insulating material used between metal layers in dual-Damascene copper interconnect stacks. But in practice, the struggle to make low-K materials ready for production has been extremely arduous.
This Netseminar will look at one success story from that struggle: a joint effort amongst a number of players. We will trace the story from its beginnings, the original motivation for low-K materials, through development of one material, the process integration that brought it to ICs, and the front end design work and back-end package and test work that made it production-ready. Attendees will see what really goes into a materials change at a major process node, will get tips for evaluating a low-K process, and pointers for deciding whether they need low-K materials at all. Best of all, you can interact with our panel to get the details.
Moderated by Ron Wilson, EE Times Editor, Semiconductors
Sponsored by TSMC
The role of distribution in system design
November 13, 2003; 11 am PT/2 pm ET
A key differentiator that electronics distributors tout is their ability to provide customers and suppliers with high quality design services to complement their demand fulfillment role. That is, their ability to add value to the design chain by working with customers early in the design process to recommend specific semiconductor supplier and product solutions. Indeed, distributors have made significant investments in myriad design services over the last few years, including investing in armies of field application engineers (FAEs), and boosting their online design offerings. Are these investments paying off? Are the services aligned with the customersý needs? What additional design services should they offer? EE Times invites you to join a panel of industry executives in a discussion on the value distributors bring to the design party.
Moderated by Bruce Rayner, Editorial Director and Publisher, EBN
Sponsored by Avnet
FPGA and EDA: Working Together
November 20, 2003; 11 am PT/2 pm ET
"Increasing complexity of FPGAs requires ASIC like tools. Is the industry ready?"
As FPGAs grow in complexity, designers must overcome the same challenges presented by high-end ASICs, including achieving performance
requirements, long verification time, integration of IP, multi-cycle clock domains, and high speed board design signal integrity issues.
Technologies developed for high-end ASICs - such as assertion-based verification, physical synthesis, silicon virtual prototyping, power
analysis, and others - must now be made available for FPGAs.
How is the EDA industry stepping up to deliver the same quality FPGA tools that have made so many ASIC designers around the world successful?
Join Brian Fuller, editor-in-chief of EE Times, and a panel of industry experts in an on-line discussion about what it's going to take to do a complex FPGA design and how the industry is ready to reach these goals.
Moderated by Brian Fuller, Editor-in-Chief, EE Times
Sponsored by Altera
Power management in cell phones
December 4, 2003; 11 am PT/2 pm ET
Each year, the pocket cellphone includes more features and functions. No longer just a palm-sized PDA and address book, the modern cellular telephone is also an MP3 audio player, a digital still camera, a video streaming media display ý even a gaming platform. But each new feature extracts a price in terms of power consumption. How the modern cellphone gets more than 15 minutes of battery life is one of the great mysteries of analog design.
In this editorial NetSeminar, veteran EE Times editor Stephan Ohr and panel of technologists from Linear Technology, National Semiconductor and Texas Instruments will explore the design issues associated with cellphone power management. The panel will review voltage regulator topologies that promote low noise and efficiency, describe the microprocessor handles that enable power-saving sleep modes; and discuss semiconductor integration techniques and processes that enable power conservation in handheld devices.
The NetSeminar will conclude with a summary statement from David Brooke of Dialog Semiconductor, the NetSeminarýs sponsor, then weýll offer ample time for viewer questions and answers.
Moderated by Stephan Ohr, Analog/DSP CMP Electronics Group Editorial Director
Sponsored by Dialog Semiconductor
When Analog and Digital Co-exist on One Chip:
Advanced Data Conversion Architectures
December 11, 2003; 9 am PT/12 pm ET
Data conversion technology is a vital element in a wide variety of
new-generation applications ranging from communications to consumer goods. Data converters must constantly evolve to meet stringent new system and market demands for higher accuracy and speeds, and lower-power and cost. In many modern systems, data converters are one of the key signal processing elements and are relied-upon to enable next-generation system performance and features. But how will these intricate mixed-signal devices meet the needs of the digital future?
In this challenging and instructive EE Times Editorial NetSeminar, a panel of key technologists will share their insights on future trends in data conversion technology, the evolution of converter architectures, and the prospects of upstream/downstream signal chain integration.
Stephen Ohr, Analog/DSP CMP Electronics Group Editorial Director, will moderate this enlightening discussion to explore the state-of-the-art in data converters today and provide a unique view of the roadmap to their future.
Moderated by Stephan Ohr, Analog/DSP CMP Electronics Group Editorial Director
Sponsored by Analog Devices Inc.
Securing the Mobile Environment: From Front to Back
March 17, 2004 / 11 am PT/2 pm ET
Assuring secure networking for mobile PDAs and handhelds involves far more than guaranteeing an encrypted over-the-air interface. Enterprise managers want to make mobile devices regular nodes in corporate networks, and thus want to ensure local data storage, secure authorization and authentication procedures. The optimal solution may be full hardware PKI and tamper-proof module support in a smart-card format, though smart cards to date have proven popular only in Europe. Can a similar solution be adopted for the North American market? Are there appropriate roles for software-based firewalls or VPN gateways?
Sponsored by Renesas.
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