Though the value of circuit editing is well-established, its benefits often are not fully realized because design and manufacturing practices do not adequately consider the circuit-edit process. Circuit edit-the practice of rewiring a circuit after fabrication as part of the product development cycle-allows designers to implement and test design modifications without repeating the wafer fabrication process. Cost savings-a new set of masks alone can cost over $100,000-and, perhaps more important, time savings (a few hours instead of many weeks) allow manufacturers to bring new products to market sooner and more efficiently.

FIB systems for circuit editing use a finely focused ion beam (FIB) to remove and deposit material in the circuit with nanometer-scale precision. Using an FIB, the editor can connect and disconnect circuit elements to correct logic faults or improve operational speed-that is, as long as he or she can find and access the elements and nodes that need modification. In advanced designs with up to nine layers of metal between the front side of the circuit and the transistors, finding the areas of interest and gaining access to them are nontrivial matters. More to the point, they often do not receive sufficient attention from circuit designers and manufacturers, making valuable edits difficult or impossible to perform.

Access, navigation

Many of these problems can be avoided by simply including editability along with manufacturability in the definition of design rules. In general, the rules must address two aspects of editability: access and navigation.

FIB cross-section through a previously drilled hole (at center) has 30:1 aspect ratio, but 10:1 holes are faster and easier to make.

Designs must allow adequate access to all critical circuit nodes. For front-side edits (wire bond mounting), access may consist of bringing the signal to the surface through the metal layers or ensuring a clear FIB path to the node through any intervening layers. FIB systems are capable of milling holes with aspect ratios (depth to diameter) of greater than 30:1. However, these can be difficult and time-consuming; 10:1 is a more reasonable specification. The same considerations apply for backside access, though the transistor layers must also be considered. Advanced designs often include unused transistors in the layout of the chip. These can be saved as spares, to be used as needed in the edit process, or as filler to improve process performance by creating a more uniform feature density across the circuit. In either case, unused transistors must be readily identifiable as available or expendable.

Sizing refers to increasing or decreasing feature dimensions-line width, for example-to accommodate process requirements, as opposed to design/performance requirements. Designers may specify allowable sizing ranges, leaving the final dimensions up to process engineers. Precise dimensions may therefore be unavailable in the design data that's used to plan and execute the circuit-edit operation. A line that is 10 percent wider than the design may cause failure of an edit that otherwise would have been successful. Sizing latitude must be considered in planning for edit access and, if possible, actual sizing data should be available to the editor.

Dummy lines are often included in metal layers to optimize the planarization process by providing a more uniform layer composition. Because the lines are not functional, they are typically added when the mask set is generated and not included in the circuit layout. Though the lines themselves are not a barrier to FIB milling, they can complicate endpoint detection in the milling process.

Connection to the line at left has been severed and a new one created to the right. This relatively simple edit was possible because design provided nearby access to the critical node.

Endpoint detection-that is, determining when to stop the FIB milling operation-is usually performed by monitoring some signal from the operation that is dependent upon the composition of the material being milled. For instance, the stage current will increase when the material the beam penetrates is a grounded metal feature. The existence of metal features in the circuit that are not included in the layout can lead to errors in endpoint detection. Though dummy lines are typically not included in the layout, they are usually added according to strict rules. These rules must be available to and accommodated by the FIB editor.

Looking for landmarks

Navigation pertains to the editor's ability to find the features needed to perform the circuit modification. Advanced circuits consist of many millions of features that all look pretty much the same. More often than not, the desired feature is not even visible from the surface and lies hidden by multiple layers of interconnect. FIB systems for circuit edit can typically overlay the design layout on the circuit image. They include sophisticated navigational capabilities that allow the editor to identify and move to a physical location based on the design layout or the circuit netlist. A laser interferometer system can guide the stage to a designated location with deep-submicron precision.

But all is for naught without some navigational reference. In front-side editing, easily recognizable landmarks are often available in the form of test structures and alignment fiducials. Even these may be inadequate on large dice if they are far from the feature of interest. Design rules must incorporate positional references distributed throughout the circuit to facilitate fast and accurate navigation.

Navigation is more difficult in backside editing. Only a small region of the circuit is exposed and it typically will not include identifiable landmarks. Infrared cameras that can see through the silicon substrate help with rough positioning but do not have the resolution required for fine positioning. Distributing reference features throughout the design layout, including the active layer, allows accurate navigation.

A final navigational issue arises from the physical distortion of the circuit, usually induced by forces exerted by the adhesives used in packaging. Clearly these need to be considered in engineering the package but they may be difficult to control and indeterminate in their effects. Once again, the inclusion of local navigational references is critical.

The debug function is the last step in the production cycle and it is often distant both physically and technically from the designers. The current trend toward fabless design and foundry fabrication only increases the distance between designers and editors. Attempts to push editability concerns upstream to the design function can meet considerable resistance.

Nicholas Antoniou is director of design debug at FEI Co. (Hillsboro, Ore.).