Sub-100-nanometer technology nodes exhibit increased subthreshold leakage currents. As a result, total power consumption for these technology processes will be dominated for the first time by static leakage power. At the 90-nm node, leakage power will be 50 percent of total power.

Solutions that reduce leakage power are primarily technology- or process-specific, and design-specific. With the former method, the manufacturing process is controlled so that the threshold voltages of transistors in critical paths of a design are different. Typically, the technology library will contain cell types of two threshold voltages. With this method, critical timing paths utilize low-threshold cells that leak more and are faster while paths that have sufficient slack utilize high-threshold cells that leak less and are slower.

A major semiconductor manufacturer recently announced the creation of a high-k-gate dielectric as a substitute for the traditional silicon dioxide, thus enabling the design of less leaky transistors. But this particular solution will not be in production until 2007 for the 45-nm node.

Contemporary low-leakage design techniques include the application of body bias, in which the substrate or body of critical-path transistors (both n- and p-type) are connected to a bias voltage to control the threshold of the transistor. For idle modes, reverse bias is applied, causing the threshold voltage to increase. As a result, leakage current decreases and the performance of the device suffers.

Under forward-bias conditions, the threshold voltage decreases, leakage current increases and the device's performance improves. This method requires additional bias voltage pins for the cell and a body bias controller/generator to regulate the body bias voltage supply.

Other low-leakage power design solutions include stack forcing, in which a single transistor is divided into two or more transistors to increase resistance for leakage currents, and the use of high-threshold sleep transistors that turn off inactive blocks of logic.

Dynamic power reduction techniques are still important. Dynamic power is proportional to the square of the supply voltage and directionally proportional to load capacitance. Therefore, voltage and technology scaling yield excellent dynamic power reduction. Other techniques include gated clock and architectural methods to reduce switching activity. Voltage islands and clusters also enable the use of reduced voltage supplies to blocks of logic to reduce total power consumption. This particular method requires a divided power grid as well as level shifters for logic paths that cross low-voltage to high-voltage boundaries.

Nonlinearity in the form of varying operating conditions is now of increasing concern in the design and manufacture of sub-100-nm designs. Near-term concerns include variability of the power grid (IR drop), temperature gradients and reliability concerns like electromigration. Low-power design techniques increase the impact of variability by increasing sensitivity to multiple voltage supplies and sensitivity to temperature.

On the heels of these nanometer effects are process- and layout-induced variability that can significantly impact final yield. Intradie and interdie process variation increases in small-geometry technologies. The result is unpredictable timing characteristics that will lead to drastic reductions in yield.

Worst-case/best-case analysis exacerbates process-related variability by artificially constraining the design in a manner that robs it of performance while lengthening the time required to tapeout, and may also reduce yield. With the continued reliance of optical correction technology for the creation of nanometer structures, layout variability will also impact yield.

Some structures may be inherently prone to manufacturing defects. Next-generation statistical analysis tools will be required to solve these types of design-for-manufacturability issues. However, analysis solutions are available today for the near-term concerns of IR drop, multivoltage design styles, temperature gradients and reliability.

The nanometer effects described will require examination of designs at multiple processes, voltages and temperatures for power, timing and signal-integrity analysis. To determine direct correlation to silicon, Spice analysis is required. It is impractical to consider the use of Spice simulations for full-chip analysis, however. Therefore, compact and accurate models that mimic the behavior of silicon are required. Historically, these models have been table-based data repositories that were captured by running Spice simulations at specific processes, voltages and temperatures. The most commonly used libraries describe timing, power and signal integrity with these nonlinear tables.

Table-based models sufficed for sub-100-nm designs. However, low-power design styles, IR drop timing analysis, multivoltage designs, body-biased designs, and the analysis of signal integrity with varying supply voltages and temperatures will require equation-based models. These equation-based models must capture variability with respect to voltage and temperature. Voltages can include multiple supplies such as voltage islands and clusters, and body bias voltages for both n- and p-type transistors.

The standard library format for timing, power and signal integrity has been extended to support equation-based models such as scalable polynomial models. These models describe a Taylor series polynomial that can include such multiple variables as slew, load, multiple voltages and temperature. The order of the polynomial is controllable and the measurement range can be divided into domains to increase the accuracy of the resulting model.

The Silicon Correlation Division of Magma Design Automation has performed extensive analysis of equation-based models for full-chip sign-off analysis for timing, power and signal integrity. When algorithmically curve-fit with the appropriate sample data, polynomial order and domains, equation-based models correlate quite well to silicon and capture the nonlinear behavior of sub-100-nm technology.

One of the key benefits of equation-based models is the ability to model a variety of operating conditions. This capability will enable advanced variable-based analysis that examines designs for a range of worst-case to best-case conditions. Equation-based models also enable sign-off of a particular design under any chosen voltage and temperature condition. When designers begin to use equation models that are correlated to silicon, they and their tools will be able to predict in advance the actual behavior of manufactured chips.

Jay Abraham is manager, Product Marketing, in the Silicon Correlation Division at Magma Design Automation Inc. (Santa Clara, Calif.).

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