As technology nodes shrink to 90 nanometers and below, chips become much more difficult to manufacture. In-die process variations increase substantially at 90 nm — even more at 65 nm. If these effects are not modeled accurately, the potential for silicon failure at 90 nm and below is very high, and the associated cost for respin of the chip is prohibitive.
Synopsys and NEC Electronics Corporation have been engaged in collaborative research since 2001 to determine how best to model these in-die process-variation effects for 90-nm designs. Research results proved that accurate modeling of in-die process variation requires efficient calculation of local density. Also, an extraction engine based on Synopsys' ScanBand architecture proved not only the most efficient choice for local density computation, but also scaled with design sizes and technology nodes. Since in-die process-variation effects increase with shrinking design sizes, such scalability is becoming a must-have.
By modeling in-die process variation in the design flow using the scalable ScanBand solution, designers have been able to calculate variations of copper line width and thickness, and compute resistance/capacitance with subfemtofarad-accurate correlation to silicon. This article will look at how these semiconductor manufacturers manage in-die process-variation effects today using the ScanBand architecture.
Thickness, width variation
Width variation of a critical wire segment-also known as selective process biasing-is primarily determined by the segment's width and the spacing to its neighbors. Process engineers measure width variation in silicon and create a two-dimensional table to represent the change in width as a function of width and spacing. This table is incorporated in a process-technology file the capacitance-and-resistance extraction engine uses to account for the effect of width variation.
Thickness variation is a more complex phenomenon. At 90 nm, thickness variation can be up to 30 to 40 percent of the nominal thickness. This large variation can significantly affect resistance and capacitance of a wire and lead to severe timing or signal integrity issues. Thickness variation is influenced by process maturity, the location of the metal layer in the process stack and other process operating conditions.
From a modeling perspective, thickness variation is primarily determined by local density. In addition, the width of the critical wire segment and the spacing to its neighbors play a secondary role in determining the extent of thickness variation.
Accuracy of thickness-variation modeling depends on the accurate calculation of local density. However, it is nontrivial to accurately calculate the range of influence for density-based thickness variation. (For the purposes of calculation, density-based thickness variation is expressed in terms of the size of the density box around the critical wire segment.) Nevertheless, an accurate method for local density calculation has been used for production tapeout.
Though it is nontrivial to determine the size of the density box for calculating local density, the density calculation itself is straightforward. Given that the density box represents the area around the critical wire segment used for calculating local density, a density box should typically extend to cover any neighboring wires that can influence the thickness of the critical wire segment. A first-order approximation of the size of the density box is the diameter of the CMP pad.
However, analysis of silicon measurements has shown that one cannot choose a single box to calculate the local density accurately for modeling thickness variation. It was found that wires farther away from the critical wire segment do not contribute to thickness variation as much as the wires that are closer. This implies the existence of a weighting function. The thickness variation can, therefore, be efficiently modeled as a rectangular prism.
By means of this process, it's possible to derive the effective local density (Deff) of a wire segment and its thickness variations by calculating Deff as a weighted average density, where the weight decreases as the distance from the critical wire segment increases. Density is calculated for multiple boxes; Deff is then computed using the following equation:
Deff = Sum d(Xi)*w(Xi)
where, Xi is the size of the density box, w(Xi) is the weighting factor and d(Xi) is the density for that particular box.
The number of boxes (i), their size (Xi) and the weighting factor, or w(Xi), are specific to a given process and are typically derived from silicon measurements by the semiconductor manufacturer's or foundry's technology development group.
The calculation of the effective local density requires an efficient density calculator based on the ScanBand architecture, which can simultaneously calculate the density of multiple boxes.
Thickness variations of on-chip interconnects at 90 nm are by far the most critical-and difficult-in-die process effects to model, requiring a multiple-density-box approach to ensure the highest accuracy of results. This approach has been used in production and has shown good correlation to silicon. (See also NEC Electronics Corp. web site.).
Bari Biswas is research and development manager at Synopsys Inc. (Mountain View, Calif.).
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