To surmount this challenge and alleviate these concerns, semiconductor vendors must provide devices with integrated 10 Gbit/sec serial links that are well isolated from all the noisy digital logic so that the integrity of the serial links can be maintained. In addition, the integrated 10 Gbit/sec serial links need to effectively traverse complex board environments.

So, what are the techniques for designing robust 10 Gbps serial links that can be effectively integrated with digital logic and still able to meet all the off-chip board and connector requirements?

While widespread growth in the 10 Gbit/sec market has been slow to develop, the variety of applications in need of increased bandwidth illustrates that eventual adoption is inevitable. The larger question in the 10 Gigabit market is not if it will take off, but rather when. By addressing the concerns system designers have regarding the difficulty of designing robust serial links at these speeds, and by providing dramatic improvements in power and cost, semiconductor vendors can be an enabling force to drive increasing adoption of this new technology.

The 10 Gbit/sec datacom market is poised for growth, with formal ratification of the 10 Gigabit Ethernet standard complete and a variety of viable optical modules reaching the marketplace. The rapid proliferation of Gigabit Ethernet ports over the last four years has provided a base of data ports rapidly finding themselves in need of higher speed aggregation, and the rate of adoption continues to accelerate. The rate of Gigabit Ethernet port installation is expected to grow by approximately 5 million in 2003, with further acceleration of growth of 8 million in 2004 and 12 million during 2005. This rapid growth curve, driven by the enterprise and metro segments, will drive a continued need for aggregation to 10 Gbit/sec.

The storage market has been presented with a variety of new standards, as 10 Gigabit Fibre Channel, iSCSI, InfiniBand and 2 Gigabit Fibre Channel aggregation technologies all jostle for position in this exciting space. And while the telecom / SONET markets have been the fastest to adopt 10 Gbit/sec signaling via an installed OC-192 base, any efficient increases in port density require smaller form factor modules with lower power and cost requirements in order to drive additional volume.

In all of these markets, the trend is the same: the need for 10 Gbit/sec systems is real and present, but is dependent upon the successful addressing of cost, power, and technical challenges.

Today's optical modules are driven primarily by the development of multi-source agreements (MSAs), specifications defined by a consortium of companies in order to define common, consistent implementations of optical modules. These agreements encourage interoperability and successful operation, and help to drive implementation towards common goals. By standardizing in this way, system vendors can move forward more aggressively with development efforts, accelerating the growth of new markets.

Optical modules based upon the 300-pin and 200-pin MSAs are present & common today. However these implementations impose significant board space requirements due to their parallel system-side interfaces and are typically quite power hungry.

The XENPAK MSA introduced the use of XAUI signaling as a 10 Gbit/sec optical module system-side output. By reducing the width of the system-side interface from 16 bits to 4, XENPAK modules are able to reduce form factor, power and cost. However, this has proven to be largely a stopgap technology, as second-generation module standards XPAK and X2 have followed rapidly behind and are ready for imminent implementation. These competitive modifications to the XENPAK agreement eliminate the need for a physical cut-out from the line card board, and further optimize form factor and power consumption.

The dramatic next step, however, belongs to the upcoming XFP agreement. Due for ratification in February, the XFP MSA defines a module providing a full speed 10 Gbps electrical signal as its system side interface. By eliminating serial-to-parallel conversion within the module, XFP modules will require as little as one fifth the space and one half the power of earlier modules, while dramatically reducing cost.

Most importantly, this approach enables an increased density of 10 Gbit/sec links, and simplifies the implementation of multiple-port line cards. However, by removing the SerDes from the module, the use of XFP requires the system designer to manage 10 Gbit/sec signals outside of the module.

The XFP agreement defines a 10 Gbps signaling protocol known as XFI, defined for the line side and dictated for performance across 12 inches of enhanced FR4 material and a connector. While intended only for operation with the XFP modules at this point, this signaling standard may serve as the basis for future development of system-level 10 Gbit/sec signaling and deserves close attention.

Integrating links

Silicon device constraints associated with this new signaling are many and varied. Foremost among these is the need for increased silicon integration. Once raw performance has been achieved, the next frontier is consistently density. An efficient step towards enabling increased line card bulkhead density is the integration of multiple links within the semiconductor components on the line card. This challenge requires that coupling, inter-symbol interference, and crosstalk effects between the channels be kept to a minimum. Verification of the ability to manage this challenge requires a full silicon implementation of multiple-channel 10 Gbit/sec links within a single device.

Meanwhile, if 10 Gbit/sec links can be successfully integrated with large quantities of digital logic, discrete functionalities can be combined, and larger portions of the system may be addressed by individual semiconductors. Furthermore, integration of independent steps of the signaling process can eliminate intermediate interfaces altogether, further saving board space, pin requirements and power consumption. Integration of this type requires that precise care be taken to ensure that the analog transceiver functionality be fully isolated from digital signaling. As with integration of multiple channels, silicon verification of analog functionality with digital switching noise is the only way to truly ensure success here.

Another key top-level challenge lies in minimizing power consumption. Implementation of multiple-port line cards requires an optimized component power budget per channel in order to attain a viable power budget for the system. Both within the optical module and on the line card, reducing semiconductor power consumption is increasingly viewed as a primary contributor to system success.

Device form factor is an important constraint. This is certainly the case in the cluttered world of line cards, but is especially crucial in optical module design, as the available real estate within the module itself is at a premium. This is, however, balanced with the need for cost-effective implementation of packaging technology. The use of mainstream packaging techniques, such as standard plastic BGA packages, can help to address the need for a small footprint while enabling a lower overall system cost.

A key factor in addressing these challenges is the selection of device process technology. A variety of exotic process technologies such as SiGe, GaAs and indium phosphide offer the ability to achieve higher performance than can be obtained on more mainstream deep-submicron CMOS technologies. However, in order to obtain this advantage, these exotic process technologies require tradeoffs in cost, power consumption, reliability and limited integration potential. The use of CMOS process technology enables integration of multiple channels, and integration with digital logic and also provides significant power consumption benefits. As such, once functions prove to be attainable within CMOS from a performance standpoint, CMOS provides an important enabler to the shift to high volume production implementations of 10 Gbps functions.

This is further enhanced by implementation in standard, volume-production flavors of available CMOS processes. In order to ensure a rapid ramp to high yields, reliable manufacturability, and large volumes, the use of generic versions of advanced process technologies at major industry-leading foundries is advised.

A key challenge that encompasses elements of all of these is cost. There is, at this point, significant elasticity present in the 10 Gbit/sec market, and reductions in the cost of the elements of these systems will therefore be a key motivator in enabling high volume production to begin.

Each of the challenges must be met in a way that both addresses the technical constraints, and maintains production-ready cost points. High-scale integration, inexpensive packaging and process design, and careful management of power consumption will all help achieve this goal.

A crucial element to successful semiconductor design is a diligent and thorough modeling approach. Precise physical design provides a path to a deterministic product development approach, which in turn enables important performance metrics to be achieved in first silicon. Accurate modeling of interconnects, including skin effect and parasitic inductance, enables proper alignment to specifications to minimize device power consumption. Only by fully modeling every aspect of the circuit, including the transistors, I/O pads, package and signal medium, can the benefits in terms of design re-use and fast time-to-market be realized.

Another important technique for design at these data rates: the use of inductor elements as a component of on chip clock lines. In order to ensure robust capabilities at the necessary levels of performance, the introduction of embedded inductors provides a means of balancing what would otherwise be a purely capacitive and resistive signaling path, thereby reducing signal loss.

Care must also be taken for circuit layout of device clock lines. When clock lines cross 10 Gbit/sec data traces on separate layers of metal within the device, it is necessary to ensure that the clock line traverses both the positive and negative arms of the data signal. Furthermore, these signals should cross one another at right angles. In this way, noise introduced by the clock signal will only affect the common mode, allowing improved noise rejection and minimizing crosstalk between the clock and data signals.

Implementation of equalization techniques to overcome bandwidth limitations can be an important consideration as well. This can be a necessary component in order to overcome the varied sources of signal impairment that can limit performance, including dielectric losses, reflections at connector points and crosstalk between independent signals. The choice of whether equalization is required, whether it is needed at the receiver or transmitter ends of the connection, and the details behind implementation all need to be carefully examined for a given system.

From a system point of view, addressing the challenges introduced by 10 Gbit/sec serial signals traversing the line card requires careful management of a number of important criteria.

Within the device package itself, implementation of the product within a standard plastic BGA package is an important design goal in order to address the constraints laid out earlier. This package technology has significant advantages, due to the mature and developed manufacturing processes and the resultant improvement regarding reliability factors. In addition, as a standard mainstream technology, cost is minimized while the large supplier base maintains the ability to work with multiple sources.

In order to achieve this goal, two independent aspects of the device design must be addressed. Strong signal integrity and packaging capabilities can allow for a robust design within the device substrate itself, ensuring that specifications are met without the need to resort to more exotic packages. In addition, low power consumption is an important factor yet again in order to ensure that expensive high thermal conductivity packages are not required.

Via design

From a board level viewpoint, a number of factors must be met. Proper design of circuit vias, in order to transition signals from one layer of the circuit board to another, is an important consideration at these data rates. The most common and inexpensive approach to via construction is the use of the through-hole via, which drills through all of the layers of the pc board. Should a signal be routed from the top layer of the board to the next adjacent layer, the portion of the via below that second layer will not be a portion of the electrical path, and due to the high frequencies of this signaling, will form a transmission line stub. A stub of that length on a common 16-layer pc board can reduce the characteristic impedance as seen by the data signal and therefore cause noise-inducing reflections, deteriorating signal integrity.

A recommended approach will be to route signals from the top of the board either to the bottom layer of the board, or to layers very near the opposite side of the board in order to minimize the length of the remaining stub and reduce the resultant reflections.

Additional considerations must also be applied for via design. In order to minimize impedance discontinuity, other factors, such as the size of the drill hole, the via pad, and ground clearance must be carefully considered. This attention will help ensure the high quality of these high-speed signals, and will help manage the use of a via with a minimum stub.

Finally, at data rates of 10 Gbit/sec, the parasitic effects of the capacitors used for AC coupling become another effect that cannot be overlooked.

One illustration of this is the importance of capacitor size. Through experimental results at Aeluros, it was found that the size of the capacitor actually has a larger impact on signal quality than price. An inexpensive capacitor in a 0402 package provided improved performance over a significantly more expensive version in a 0603 package and would therefore be recommended for 10 Gbps links.

Widespread adoption of 10 Gbit/sec systems requires that challenges in implementation, cost, and power be faced and addressed, at the silicon, package, board, and system levels. Through attention to the factors outlined here, and careful application of a variety of design techniques, these challenges can be met and addressed head on.

Engineers at Aeluros have completed development and characterization of the Bobcat device, a test chip combining four independent 10 Gbit/sec channels within a single device. Implemented in standard 0.13-mm CMOS silicon and a common plastic BGA package, the Bobcat device also incorporates circuitry to generate noise equivalent to 1 million gates of digital logic. Through devices like this, achievements in integration, process, power, packaging and performance have all combined to provide an illustration that the techniques described can provide a successful, robust solution to the 10 Gbit/sec challenge.

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