This time around, however, designers will find far different requirements at the line card level. With carriers looking to finer-grained service-level agreements, designers are being asked to provide more finely grained traffic-management and switching capabilities. To meet those requirements, they must provide the ability to provision traffic on a port-by-port basis at the chip level, a topic AMCC examines in its contribution to this week's In Focus.

In addition to any-port provisioning, carriers are calling for line cards with more ports and more functionality, a need that requires chip designers to push the limits of Moore's Law in their OC-192 designs. In its article, TranSwitch Corp. looks at the impact of Moore's Law on achieving the port density and switching requirements of today's high-speed line cards. At the same time, Parama Networks and Ample Communications look at how new levels of integration are changing the functionality and capabilities provided in 10-Gbit line cards.

Of course, provisioning and integration aren't the only concerns for high-speed line card designers. As engineers from IDT Inc. point out in their article, designers must implement such new schemes as multidatabase lookups to prevent slowdowns in memory bus speed. At the same time, authors from Zarlink Semiconductor point out that understanding jitter is a key to assuring strong OC-192 line card performance.

In all cases, designers will find a more fruitful market for high-speed line cards than they did a few years back. And they will also find a host of new requirements, placing new demands at the chip, board and system levels.