The "universal port services" aggregation architecture comprises four key device-level hardware elements: a high-speed multicore NPU with integrated TM coprocessor; a protocol controller capable of handling both high-level data link control (HDLC) and ATM; multiple highly channelized framers that can handle up 8,000 DS0s (64-kbit/second links) per device; and quad clock and data recovery with multiple line interfaces aggregating up to OC-48 bandwidth per device. The devices are designed and tuned to work together using both glueless logic and industry-standard interfaces, such as SPI-3 and SPI-4.2.

Framer devices will need to accept any combination of up DS3/E3 copper connections or OC-3 and OC-12 optical interfaces and support granular switching down to the STS-1 level with standards-compliant framing, overhead management and termination down to DS0s. A single OC-12 will have up to 8,064 DS0s, from a variety of clients. The architecture will need to support additional framer devices in order to increase capacity.

Scalable line card designs can provide port capacities for up to 32,000 flows and can be flexibly provisioned for 2.5 Gbits/s with a mix of standards-compliant tributaries up to 32,000 DS0s, 1,344 T1 lines, 48 T3s or 16 OC-3s. The ability to support a large number of different-size pipes, coupled with multiprotocol programmability, lets line cards provide universal port services that conform to user requirements while assuring high bandwidth utilization.

The traditional architectures of dedicated data paths for each service require switching logic and devices to support full capacity of bandwidth for each protocol. Unique design of the protocol controller, supporting multiple services for each TDM channel, provides an efficient "black box" bridge between TDM- and packet-based protocols. It is equally able to aggregate and terminate timing-sensitive cell traffic (such as ATM) and packet traffic (HDLC).

With support for up to 2,048 simultaneous channels of packets or cells, the protocol controller allows for a continuous nonblocking flow of heterogeneous traffic between the NPU/TM and the framer array. Multiple devices can be used in tandem to increase the channels or customers supported in the 2.5-Gbit/s connection.

Close interaction needed
A key for achieving the required performance is close interaction between the NPU/TM and the individual channels in the protocol controller. Such interaction gives the NPU direct visibility into all of the queue depths in the protocol controller, allowing on-the-fly protocol provisioning and policy-based processing decisions with maximum granularity while minimizing the risk of overrunning or underutilizing the available buffer memory. An architecture based on supporting the mix of Layer 2 protocols with the programmable NPU enables the software-assigned protocol support and integrated network management for the entire solution.

Such a multiservice aggregation architecture also serves the continuing evolution of high-speed core transport services. A high-touch TM coprocessor is vital for managing and shaping very large numbers of individual flows on the aggregation side. On the transport side, the emphasis is more on efficient transport of converged Internet Protocol traffic using such mechanisms as multiprotocol label switching with DiffServ-type quality-of-service.

A typical transport profile over OC-192 or Gigabit Ethernet links might be eight service classes and 16,000 queues, which would call for high-speed but not necessarily high-touch traffic management. The key would be the ability to shape traffic and pack/unpack MPLS at the edge aggregation points that constitute the on and off ramps for high-speed core transport.

In an MPLS environment, incoming packets are initially assigned labels by an edge router, which enables the packets to be more efficiently handled by MPLS-capable routers at each point along the forwarding path. Each MPLS label consists of a short fixed-length value within each packet's header that identifies a forwarding equivalence class, which tells the router how to handle the packet.

The edge aggregation architecture enables flows from every port to be efficiently prepared for high-speed transport using MPLS, because MPLS label processing is integral to the network-processing pipeline for every port on every line card. The software programmability built into the universal port architecture provides a degree of future-proofing for carriers.

Universal port services mean fewer separate line card designs, thereby enabling vendors and carriers to benefit from lower development costs as well as reduced inventories and logistics expenses. The ability to soft-configure line cards remotely also allows carriers to reduce their operating-expense requirements by provisioning services without the need for truck rolls or field technician time.

By providing up to 64,000 bidirectional flows per implementation, the architecture enables vendors and their carrier customers to configure multiservice systems for optimal utilization of limited space and power within a variety of deployment scenarios.

Amit Banerjee and John O'Neill are staff field applications engineers at Applied Micro Circuits Corp. (AMCC; San Diego).

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