Communications service providers are under pressure to meet growing bandwidth demand using existing network infrastructure. Whether their current infrastructure is based on Sonet, SDH, Ethernet or asynchronous transfer mode, service providers must continually evolve their networks to carry increasing traffic, and they will be required to do so for years to come.

For service providers to be successful, system developers must employ creative new approaches to design efficiency. This efficiency comes down to how many interfaces and how many customers can be supported on a single line card. The more interfaces, the more customers, resulting in increased revenue per system.

The number of interfaces that can be supported on a single network line card is directly affected by the efficiency of the silicon in terms of speed, space, power consumption and port density. In a traditional line card design, the physical layer, framing/pointer processing layer and data link processing layer have been delivered by silicon vendors as separate components. A large number of components directly correlates to a large number of chip-to-chip interconnects.

Because device I/Os typically consume most of the power required by a device, this ultimately leads to higher power consumption. Increased power consumption in turn results in more heat dissipation and thermal system-level limitations. Also, multiple components take up a larger footprint on a circuit board, increase design complexity and reduce reliability.

The answer is higher component-level integration. One approach is to integrate multiple instantiations of similar logic in a single device-for example, multiple framers or multiple transceivers. An alternative is to integrate different functionality in a single device-for example, a framer and a transceiver. The approaches have been combined in some cases.

When pondering integration, architects must consider technical and financial trade-offs. Two limitations are the process technology used and the need for a practical die size, to assure a cost-effective device that can be easily manufactured.

Today, the most common process technologies for new designs are 90- and 130-nanometer CMOS, where the die size should not exceed 15 x 15 mm and for cost reasons should be kept to under 12 x 12 mm. From a process technology standpoint, high-speed-10 Gbit/second and higher-analog design may require higher-cost 0.25-micron silicon germanium or 1.5-micron indium phosphide process technologies. High-gate-count digital design, meanwhile, is most cost-effective in high-density CMOS process technology. Combining these technologies in a single component is not practical, so separating these two functionalities into discrete components is the only feasible solution.

In recent years, communications silicon vendors have introduced components that have integrated higher numbers of ports and more functionality across multiple functional layers. Market acceptance has varied. For example, attempts were made to integrate optics, transceiver, framer and mapper into a self-contained optical module. The solution, although technically sound, was not cost-effective, because the many framer configurations resulted in lower volumes per solution.

Another attempt was to integrate network-processing logic with framer and Ethernet media-access controller (MAC) functionality. But the die-level real estate allocated to framers and MACs limited the space available to key network-processing functions. And again the multiple flavors of required configurations resulted in lower volumes and higher costs.

The most effective partitioning separates functionality into three areas:

• Physical-layer solutions-copper or optical physical-layer interfaces such as 10-Gbit form-factor pluggable (XFP), small-form-factor pluggable (SFP), gigabit interface converter (GBIC) optics or copper connectors plus magnetics.
• Layer 1 and Layer 2 solutions-serializer, deserializer, clock and data recovery (CDR) and a framer or Ethernet MAC.
• Layer 3+ solutions-network-processing logic such as classification, packet forwarding, policing, shaping and quality-of-service.

This recommended partitioning lets system vendors mix and match the best-of-breed and most cost-effective components from different vendors. Vendors can lower costs by realizing economies of scale. For example, the same 10-Gbit/s optical module could be sold into channelized or concatenated solutions in both data and transport applications. Similarly, a framer for a given speed could be sold to multiple customers using different vendors' network processors. Finally, the same NPU design with accompanying complex software can be used in multiple applications without software changes.

The industry has realized this partitioning by standardizing interfaces among these three functional blocks. The interface between the optics and framer is defined by the Optical Internetworking Forum's XFI and SFI standards; the one between the framer and a network processor is defined by its SPI standards.

An interesting example of integration progression is the Layer 1 and Layer 2 solution, where integration occurs at both the functionality and port levels. A few years back, the physical-media-dependent (PMD) function was separated from the framer and MAC functions, and both framer and MAC were available as single-port discrete solutions. This was primarily because copper line interface units and optical serdes and CDR devices were developed in processes such as SiGe, gallium arsenide or BiCMOS, while framers and MACs were developed in CMOS.

Recent advances in process technologies and analog design allow developers to implement their analog designs in CMOS for speeds of up to 10 Gbits/s. That facilitates integration of Layer 1 PMD functions with Layer 2 framers and MACs.

Analog design limits the number of PMD instantiations that can be implemented in a single device, which in turn is the driving force behind the number of integrated ports that can be achieved on a single device. Thus, today multiport integrated Layer 1 and Layer 2 components are limited to certain configurations.

Looking at trends in Layer 1 and Layer 2 integration, designers can expect single-port PMD and framer and MAC integration in the 10-Gbit/s space for OC-192/STM-64 Sonet/SDH applications as well as the introduction of multiport 10-Gbit/s Ethernet devices. For higher speeds, such as 40 or 100 Gbits/s, designers won't soon see a PMD integrated with a framer or MAC, because of process technology differences for those applications.

Another trend is higher port count integration at lower speeds. At some lower speeds, such as DS3 and OC-3, current integrated solutions have reached an application sweet spot, driven by faceplate limitations and standard mappings into higher-order speeds-for example, mapping 12 DS3s into one OC-12.

At these speeds, further integration is not likely in the near term. At other lower-speed rates, such as DS1 and 10/100 Ethernet, designers will see further port count integration.

Marek Tlalka is vice president of marketing and product management at Ample Communications Inc. (Fremont, Calif.).

See related chart