Next-generation data movement and I/O-intensive network infrastructure equipment will require revolutionary performance improvements to meet bandwidth, capacity and scalability requirements. Numerous I/O technologies will be utilized to transfer data in multiple-gigabit-per-second serial streams, point to point through equipment backplanes.

Complementary to this is the need for a robust, scalable, distributed clock management plane. Multipoint low-voltage differential signaling (M-LVDS) technology will fill this need to support clock distribution for future infrastructure equipment.

As switch fabrics become more mainstream in all phases of the network architecture infrastructure, the need for standardization grows. Custom-designed backplanes and switch fabrics can provide differentiated performance capabilities but may not achieve the economies of scale required to provide a return on investment. Efforts are under way to standardize new architectures to enable companies to meet financial as well as performance goals. An example of such an effort is the Advanced Telecom Computing Architecture (AdvancedTCA) specification developed by the PCI Industrial Computer Manufacturers Group.

Standard interfaces

The AdvancedTCA specification is a comprehensive document that includes mechanical, thermal, electrical and power requirements for compliant subsystems. The AdvancedTCA specification provides for a variety of standardized switch-fabric interfaces, while leveraging an underlying set of core specifications for common functions. The specification supports switch-fabric implementations including star, dual star and full mesh. A full-mesh design provides the most flexible, highest-throughput implementation using a fully interconnected set of data paths between each system board.

Standards like AdvancedTCA are already emerging that will smooth the way for a broad implementation of M-LVDS as a new model for clock distribution in network equipment. This new approach is best understood if we first look at existing solutions.

As with any complex design, timing signals must be distributed throughout the different boards in each switch, router, etc. A classic approach is to have a centralized clock module distribute timing signals through the backplane to each chassis card. Older systems have used single-ended clock distribution, with differential signaling the preferred approach, as clock speed increases and signal integrity becomes more of a concern.

An improvement on the centralized clock module approach is a set of redundant clock modules, which provide reliability improvements in the case of failure of the primary clock module. When either a centralized or redundant centralized approach is used, the clock modules generally use numerous point-to-point links (one to each node) to fan out the timing signals. Often the clock signal requires further processing on each node. This processing can involve cleaning up the received signal via "jitter cleaners" or synthesizing local clocks by way of clock dividers, multipliers and phased-locked loops.

The clock distribution architecture specified by AdvancedTCA, however, represents a departure from such legacy systems. It supports star, dual-star and a full-mesh switch fabric. Full mesh is the most flexible and robust implementation. Equipment capacity is increased as each board is added to the system, rather than being constrained by a parallel-bus bottleneck or a switch-fabric hub card limitation.

AdvancedTCA also supports a flexible clock distribution approach. This new clock distribution scheme is multipoint, reliable and robust.

In an AdvancedTCA system any board can be the source of a clock signal. This contrasts with the centralized or redundant-centralized approach, where clock distribution is a dedicated function of specific clock modules. In addition, clock signals are bused between all card slots. Point-to-point clock implementations deliver a cleaner signal to each card than this bused approach; however, a bused approach provides a cost-effective, flexible solution when the use of "clock-processing" elements is prevalent at each node. With this new approach to clock distribution, each board can now be a source or sink of a clock signal, representing a true multipoint (multiple drivers and receivers) topology.

AdvancedTCA specifies a set of three separate, redundant clock buses. Single-point failures are handled by transitioning to the backup bus, with all system boards transitioning through this switchover without losing synchronization. The distributed nature of this architecture provides even greater reliability, as clock source responsibilities can transition from one board to another.

Using M-LVDS

In addition, AdvancedTCA systems provide a robust solution to clock distribution. Each board that is interconnected to the clock bus must support hot-swap (insertion and extraction from an active system) without suffering damage, and must ensure that clock interface devices are high impedance during hot-swap and while being powered.

This new approach to clock distribution requires the use of a new class of clock drivers and receivers. The AdvancedTCA specification requires the incorporation of M-LVDS technology to implement this synchronization system. M-LVDS technology is standardized in TIA/EIA-899,and provides a true multipoint capability that is ideally suited for the AdvancedTCA architecture.

Edge rates

M-LVDS requires that drivers have slew-rate-limited edges, with transition times greater than or equal to 1 nanosecond. These edge rates allow for longer stubs-as will be encountered in a bused clock environment-while they still support clock rates above 200 MHz.

To support multipoint clock distribution, AdvancedTCA requires termination of the clock bus structure at both ends of the bus. The backplane differential impedance used on clock bus lines is 130 ohms. Loading the backplane with a complement of boards reduces this impedance due to capacitive loading. The bus terminations are 80 ohms, and the resulting load seen by clock drivers is approximately 40 ohms.

M-LVDS drivers provide 11 milliamps of current, supplying greater than 400 millivolts of differential signal in heavily loaded cases. M-LVDS receivers incorporate 50-mV thresholds, providing a 2x improvement over LVDS receivers. Those thresholds, coupled with the 400-mV differential signal, provide reliable delivery and recovery of the bus clock signal.

To fully support bused clocking, M-LVDS provides contention provisions as well. M-LVDS drivers can withstand fault conditions where multiple drivers are simultaneously active. The AdvancedTCA specification includes a management layer that prevents more than one clock driver from being active at any instant.

Interchangeability of components is another important factor for system architects as they consider the design of network elements. M-LVDS clock distribution solutions support this need via standard compliance, as well as multi-source development. Texas Instruments Inc. has introduced two series of standard-compliant M-LVDS transceivers. The most recent products support 100-MHz clock distribution, as required by the AdvancedTCA specification.

Jim Dietz is a systems engineer at Texas Instruments Inc. (Dallas).

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