With individual chips approaching 50-million-gate equivalents and inception to delivery time measured in months, efficient design automation flows have become mandatory enabling technology. Few contemporary designs could be economically realized without an integrated design flow matching all the design techniques in use. But in early 2003 no flows were available with commercially targeted support for asynchronous design; without that, only a few and much smaller designs have benefited from asynchronous design.

Working with engineers at Theseus Logic Inc. (Orlando, Fla.), we have identified several asynchronous functionality gaps requiring design automation and have been working to fill them, including: language support for integrated asynchronous design; verification techniques capturing asynchronous design operating and failure modes; synthesis techniques efficiently mapping from a behavioral model to various synchronous and asynchronous design styles; and optimization techniques.

Most commercial designers of synchronous logic-based designs think in terms of VHDL, Verilog or a C dialect. All three language universes were designed with the predominantly synchronous design style in mind. Synthesis packages from IEEE all assume one or more clocks with interleaved combinational logic. While innovative approaches exist to use contemporary VHDL, Verilog and C for asynchronous design components, they add burden for the designer. In many cases, asynchronous design increased the volume of code that needed to be written, debugged and maintained by up to 10 times relative to synchronous, register-transfer-level design.

Excellent unique languages have been developed for efficient asynchronous design, including CAST from Caltech, Balsa from the University of Manchester and Tangram from Philips. While appealing in their potential for optimal use, the break from mainstream design expertise and tools they represented cost designers valuable time spent gaining expertise in the new language. In a commercial venue, development of a complete commercial design flow around a uniquely new language is prohibitively costly for most companies to create, train and maintain. Finally, since synchronous design components exist and often are the right choice for a particular usage, we concluded that a fundamentally new language embracing only synchronous design was not commercially viable.

Instead of designing a new language, we took on developing consistent extensions to VHDL, Verilog and C to efficiently support a range of asynchronous design styles operating close to asynchronous design styles. Since code volume is closely correlated to design cost, it was critical that the asynchronous design style require less source code bulk for comparable functionality than that imposed by the IEEE standard synthesizable, clocked version. To reduce training cost, specifics of a particular asynchronous design style needed to be encapsulated so that many designers could leverage the expertise of a few clockless design experts, either in-house or via licensed design style libraries from a firm such as Theseus Logic.

A set of delay-insensitive semantics that could be consistently mapped onto VHDL, Verilog and C was developed. Then the extensions were mapped into specifics of the target language to present a consistent designer view. These extensions were combined with other extensions to the base language, resulting in a VHDL, Verilog or C superset such as VHDL-X.

Clocked systems implicitly rely on arrival of a particular time to "freeze" the value of a particular signal; various asynchronous design styles utilize either explicit or implied acknowledgment to communicate that data was valid (forward direction) or that data was accepted (backward direction).

Mechanisms for persistence, analogous to clocked registers, take various forms based on the representation and acknowledgment paradigm or paradigms involved. Similarly, encoding of the same data values within a realization takes many forms depending on the asynchronous design paradigm and optimization criteria (such as design size, throughput, latency, wiring density). A global or local change in the visible packages, library or included headers allows rapid design migration from one style to another with little effect on the actual design.

Design verification techniques intended for synchronous systems omit several capabilities that are important when verifying designs, including asynchronous components.

First, simulators and formal model checkers verify timing with a single value for each delay, such as a minimum or maximum. Actual asynchronous circuits will vary, pseudo-randomly over time, exposing the design to vulnerable timing coincidences leading to potential failures.

In addition, physical components associated with boundaries between synchronous and asynchronous design components will sometimes oscillate between low and high states for an indeterminate time interval, leading to undefined operation. This failure mode, known as metastability, can be greatly reduced with suitable synchronizer design techniques such as those included in Theseus Logic's Null Convention Logic (NCL). Conventional synchronous design flows do not insert such synchronizers or estimate reliability impacts of metastability.

Hardware description language extensions supporting technology-independent asynchronous design are understandably not included in conventional clocked design tools. As a result, conventional design flows require synthesis of asynchronous designs to gates or even transistors before behavior can be debugged, lengthening the design cycle.

Synthesis and optimization tools generally do not accept design descriptions with explicit asynchrony, do not emit asynchronous design constructs and frequently require disabling of sufficient optimization functionality. These result in several significant designer effects.

One of the most serious is the inability to design at more abstract behavioral levels where designs can be captured and debugged faster. Just as critical is that reference designs can't be automatically implemented using asynchronous design techniques. As a result, basic optimization techniques available to clocked designers must be either disabled or risk optimization-induced design failures.

Many asynchronous design techniques other than NCL demand tight bounds on physical design properties. Such constraints must be respected by the physical design system. In our verification, synthesis and optimization tools we have reordered and modified the design flow so that each of the major verification (and synthesis) components efficiently addresses the additional requirements of asynchronous design. The standard Sugar assertion language requires extensions, analogous to those included in VHDL-X, to capture the additional properties of asynchronous designs.

Unique design flow components include analysis of synchronous to asynchronous interfaces (GALS tools) and technology-specific analysis, such as Orphan checking used for NCL. Virtually every component of the design flow was ultimately revised to efficiently support synchronous and asynchronous design within a common design flow.

Darpa has initiated a program to foster asynchronous design technology. This program, Class, focuses on design, design automation and demonstration systems stretching the size, speed and other limits of contemporary design. Under a phased plan, several demonstration systems are expected to exceed 50 million transistor equivalents.

Design automation has been a barrier to mainstream use of asynchronous design techniques. Limitations of hardware description languages, design verification and synthesis have presented barriers to efficient asynchronous design. Integrated design flows are now becoming available with complete support for combined asynchronous and synchronous design, letting designers develop such systems with the same or even less effort than previous generations of synchronous systems.

John Willis is the CEO at FTL Systems Ltd. (Rochester, Minn., and Chilworth, England).

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